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Level-shifter cells are removed after placement

manpmanp

Hi there!

In my design, I intend to have a power domain containing all level-shifter cells.

The Tool for synthesis is Synopsys Design Vision (K-2015.6-SP4) and the PNR tool is Cadence Innovus (v16.13) and technology ST 28FDSOI.

The steps I have taken towards this target:

1- using a clock buffer as the level-shifter component in LevelShiftDomain.vhd

2- synthesizing the design

3- CPF file containing all necessary details, such as powerDomains and their definition, all available level-shifter cells to use (define_level_shifter_cell) and rule to use them (create_level_shifter_rule)

however after place_design, cells  from level-shifter power domain are removed.

What is your suggestion to solve this issue?

  • manpmanp
    I could solve my problem by following the steps mentioned below:
    1- The level shifters are defined in the library with a specific vddi and vddo. for HL or LH check and use the necessary (both or one) one in the CPF libraries.
    2-Define the level shifter cells with define_level_shifter_cell and use the range as input and output voltage as may be needed and later match the power domains
    3-check the create_power_net for the crossing power domains contains the required ranged which has been defined previously in define_level_shifter_cell
    4-create_level_shifter_rule and think in advance about the right combination of the defined cells, defined libraries, vddi and vddo in libraries, and finally the location of placement by setting the a correct -from and -to info in this command
    5-If using create_level_shifter_rule more than once remember to use update_level_shifter_rules -names -location to force the implementation either for each rule separately or put all similar ones in the same update command

    good luck

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