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Encounter via placement rules

masserg

Good day.

I just studdy place and route procedure by Encounter and got a problem.

My foundry prohibits to locate via on thin oxide (minimal space 0.1u), but I cannot handle it by Encounter.

By IC Craftsman I can do it by rule specify:

rule IC (inter_layer_clearance 0.1 (layer_pair VIA12 FieldOxide))

In Encounter I didn't find such a solution.

In LEF file, generated by Abstract Generator, I can put VIA12 layer blockage like

ThinOxide = DIFF AND POLY1

VIA12 BLOCKAGE = VIA12 OR ThinOxide

But it works like standard VIA12 blokage with minimal space for this layer 0.6u, but I need VIA12 to VIA12 space 0.6u and VIA12 to ThinOxide 0.1u.

I didn't find Layer to Layer space rules in LEF file description.

BTW, Abstract Generator always occupies 100% of CPU even when it does nothing (just starts). What's wrong with it (version 5.1 on Linux)?

Thank you and best regards.

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