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Padring Routing

susman

Dear All,

I am currently working with back-end design of chip an getting some problems. I've added a pad-ring by modifying my synthesized netlist and I've used PVDD1DGZ/PVSS1DGZ and PVDD2DGZ/PVSS2DGZ as core and I/O power pads and I am using libraries. In the Encounter, when I use sroute to route the padring , I am getting the following warning:

**WARN: (ENCSR-1255): Cannot find any non'CLASS CORE' pad pin of net VDD.  Use 'CLASS CORE' pad pins of net VDD to create padring.

**WARN: (ENCSR-1255): Cannot find any non'CLASS CORE' pad pin of net VSS.  Use 'CLASS CORE' pad pins of net VSS to create padring.

I am new in the chip back-end design and would like to know more about routing of pad-ring and I/O power pads. Do we supply external separate power supplies for core power pads and  I/O power pads, or there is some internal power conversion and how do we route them?

Thanks,

Saleh

  • usually the padring is connected by abutment, meaning the simple act of having the pad cells placed together in a ring is what connects the padring, provided you have IO fillers in any gaps, and corner cells that continue the rails around the corners, etc. Core power and IO power are usually different voltages, and therefore different sources, but VSS is usually shared (but it can be separate - depends on the design). If you have a flip-chip, the power bumps will have to be routed to the IO pads, but sroute is not used for that. 

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