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Hierarchical flow with (some) manual place and route

jpf91

Hello everybody,

I'm new to Cadence tools and the ASIC world, so this is probably a stupid beginners question. But it's hard to find information without knowing the exact terminology so I'm hoping you may provide some keywords for further research:

What I want to do is a mostly custom layout for a hierarchical, digital design. The top level (top) is (pysically) a grid of different blocks, let's call them blockA and blockB. blockA is written in behavorial VHDL so I think I'd use the standard Genus+Innovus flow here. blockB however is written as a structural VHDL model, i.e. it just instantiates other cells (blockB1, blockB2) and describes the routing in between these cells. Now I want to manually place and route the blockB1 and blockB2 cells in block blockB. The blocks blockA and blockB shall also be placed and routed manually in the toplevel design.

So I'm wondering what tools and flows to use. Obviously for the standard digital blockA I'd use Genus+Innovus flows. But which tool/flow can be used for custom placement / routing for blockB and the top level? Does Innovus fully support this and is worth looking into the Innovus Implementation System (Hierarchical) course? Or do I have to use Virtuoso/ Virtuoso Digital Implementation for this? As far as I know Virtuoso Digital Implementation has tighter limits on gate counts? Also most Virtuoso documentation assumes schematic based design, however I'd like to use my structural VHDL to describe the hierarchy and still be able to use LVS. Is this possible?

Also, what's the correct terminology for these subblocks in a hierarchical design? Black boxes / macro (cells)? And how are these usually handled in the flow (lib / lef / gds)?

Sorry for these high-level overview questions. If there's some good high level overview somewhere (what exactly to do with which tools, which file format is used for what, how tools interact, etc.) I'd be very grateful for a reference. I know there's the iLS learning map, but it's quite overwhelming as I don't even know which tools are best to use for my usecase. I've got access to all the Europractice stuff including the iLS. So I'll be able to lookup all the details in these courses or the tool documentation. But as there's so much documentation, I'm hoping for some expert advice where to start ;-)

Regards,

Johannes

Parents

  • I believe you can still use Innovus - you will have to have LEF models for these other blocks, or if they really are black boxes, they can be defined as such early in the flow, but you'll want LEFs for them eventually. not sure if this answers your question or not. Blocks (not std cells from a library) are referred to as either blocks or macros and are represented in the database by a LEF for physical info and .lib files for timing info. There should also be a GDS of a block that will get merged in when the final design is written out as GDS for tapeout. Hope that helps....

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  • I believe you can still use Innovus - you will have to have LEF models for these other blocks, or if they really are black boxes, they can be defined as such early in the flow, but you'll want LEFs for them eventually. not sure if this answers your question or not. Blocks (not std cells from a library) are referred to as either blocks or macros and are represented in the database by a LEF for physical info and .lib files for timing info. There should also be a GDS of a block that will get merged in when the final design is written out as GDS for tapeout. Hope that helps....

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