Stats

Locked Locked
Replies 0
Subscribers 91
Views 13476
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Innovus CTS for a range of clock

Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.

How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ?

thank you for your time.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.