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Hold time violations in post layout simulation

anurans

Dear All,

I have a pipelined design that was placed and routed in Innovus in MMC view. So the setup and hold views are based on worst and best corner libraries respectively. Starting from bc_wv view, the design was incrementally optimized (pre/post CTS) and the final post route optimization was done in OCV mode. Both postRoute timeDesign (Innovus) and Primetime STA have validated that the design is free of setup (WC .sdf) / hold (BC .sdf) violations. 

But the post route simulation in NVSIM with annotated typical.sdf (extracted from Innovus after setting the design to typical view) and the post layout netlist gives me hold time violations. I've checked the clock constraints in testbench and they seem to be okay. Design does not have multiple clock domains, nor cross clocking. The simulation over the typical conditions is intended for the power analysis. Any possible explanation for this behavior ?

Thanks and BR

Anuradha  

  • Further adding to the observations: The (Warning !) violations appear with worst and best corner .sdf files as well. However out_norm[1] (The data input to the Out[1] register) signal transition seems inline with clock transition which might be the case for this behavior. But why this was not detected in post Route timing stage ? However I had clock uncertainty defines in both synthesis and P&R. Or am I missing a switch in simulator ?

     

    Thanks

  • in reply to anurans

    Hi Anuradha,

    This probably needs more investigation via timing reports/testcase. Kindly file a Case on http://support.cadence.com and we can get some help.

    Regards,

    Chetan B S

  • in reply to Chetan B S

    Hi, this was resolved. The issue was in the .sdf annotation. I hadn't specified the MTM spec correctly in sdf annotation (wheres by default typical value is used) which also leads to the wrong clk -> Q delays. 

    But I need to clarify one thing about P&R optDesign.

    1. If the design is in MMMC mode, I know by default, setAnalysisModeis in Bc_Wc mode. I started P&R with this mode and before do optDesign -postRoute, change it to onChipVariation. Then perform timeDesign -postRoute to verify setup/hold timing. Are these steps correct ?

    2. I use the bc.sdf and wc.sdf (generated after OCV + optDesign PostRoute stage) for STA in Synopsys Primetime (PT) too. When these two .sdf are used in BC_WC mode of PT, there are no timing violations. However when the PT is in OCV mode, there are hold time violations. What could be the reason for these violations to appear (which do not appear in Innovus timeDesign -postRoute) in PT OCV mode ?


    Anuradha

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