Stats

  • Locked Locked
  • Replies 0
  • Subscribers 91
  • Views 2297
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Power estimation - Genus

yenass

Hello,

I am using Genus for post-synthesis power estimation, this estimation is based on the use of the lp_asserted_toggle rates and static probability.

The idea is I am wondering due to some results when i used the lp_computed toggle rates and static probability, because 

When I build a 8 bit register like 8 DFF flip flops with an asserted clock frequency of 100MHZ (toggle rates=0.2 and static probability=0.5) with inputs asserted to taoggle rates that exceed 0.1 (more than f/2)

I get at the output of the flip flops toggle rates as the inputs for example for 0.15 i got 0.15 for the output, classically the flip flop should suppress the effect of glitch (cases where toggle_rates >0.1 in our case) 

I kindly ask you to help to understand this issue well.

Best Regards,

Yenass

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.