Low power design - Power estimations Genus - Toggle rates and static probability

Hello,

I have a problem when I used the lp_computed toggle rates and static probability, when I built an 8 bit register like 8 DFF flip flops with an asserted clock frequency of 100MHZ (toggle rates=0.2 and static probability=0.5), and the problem that I did not understand when the data inputs are with inputs asserted_toggle_rates that exceed 0.1 (more than f/2), and I got at the output of the flip flops toggle rates as the inputs, for example if 0.15 asserted toggle rates, I got 0.15 for the output, classically the flip flop should suppress the effect of glitch (cases where toggle_rates > 0.1 in our case).

Noting that, by definition: toggle rates of a clock signal is = 2*(1/T) , where T is the period in ns and 2 means 2 toggles within T (source: cadence RTL-Compiler reference guide), for a data signal at the input of a flip flop, a signal with activity factor of 1 like a clock signal toggles 2 times within 2*T so the toggle rates maximum without glitch is equal to 2/2*T=0.1 for this purpose any value of 0.1 toggle rates represent a data signal that toggles each T, so for this purpose numbers greater than 0.1 and less than 0.2 should be suppressed by a flip flop by theory, but is not the case with the tools and simulations. Note that also, putting values greater than 0.2 at the input of a flip flops gave a maximum of 0.2 at the outputs.

Thanks to help to understand why the tools gave this results.

Regards,

Yenass.