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Innovus Parasitic Extraction Compatible for Spice Simulation

anurans

Hi All,

Is it possible to annotate the interconnect parasitics (.spef and .dspf) generated (IQRC) after P&R in Innovus,  with a pre-layout transistor level netlist of standard cells in Virtuoso ? This procedure is bit similar to post-layout STA. Instead of gate level netlist, I wonder whether we can use the interconnect parasitics with transistor level netlist. Instead of doing GDS flow, can we generate accurate timing and power numbers in this way ? 

Ranayas

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