Stats

Locked Locked
Replies 0
Subscribers 91
Views 15549
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

D Flip-Flop with asynchronous reset characterization using Cadence Liberate

Hi ,

I am developing standard-library for technoloyg with few cells: NAND, NOR, NOT, LATCH, D Flip-Flop and D Flip-Flop with asynchronous reset. I am able to synthesize all cells except for the D Flip-Flop with asynchronous reset. I have simulated the design using spectre simulation and the functionality is correct.

I see no errors during the synthesis flow only some warning regarding the undefined templates for constraints.

My cell definition is as follows:

if {[ALAPI_active_cell "DFFNRX1"]} {
define_cell \
-clock { CP } \
-async { RST_N } \
-input { D } \
-output { Q Q_bar } \
-pinlist { CP D Q Q_bar RST_N } \
-delay delay_3x3 \
-power power_3x3 \
DFFNRX1

}

At the end of characterization, tool shows the warning:

*Warning* (write_verilog) : No function written for pin Q of cell DFFNRX1
*Warning* (write_verilog) : No function written for pin Q_bar of cell DFFNRX1

also in the .lib file I don't see the function for the Q and Q_bar. Could anyone help me?

Thanks

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.