How to clock gate in hierarchy?

Hi,

I am trying to clock gate a part of my design with one enable signal. It seems logical to me that instead of using the enable signal to each register inside the modules and sub-modules, it would be better to directly gate the clock high in the hierarchy.
I would like to use the special clock gating cell from the std cell library and not the generic latches and gates. Is there a way to infer the clock gating to the synthesis tools?
Is there something similar to the ChipWare library, for example, that can infer clock gating cells?

Best Regards,
Dimitrios