I'm actually designing an IP where i need to send a signal from (x1;y1) to (x2,y2) in the floorplan.
In the following, i explain how i'm actually handling with my design :
For the drivers and receivers i'm selecting 2 buffers from the timing library i'm using.
I can be brought to route the driver and the receiver in different routing metal layer (mainly i need the most top metal available)
to connect the buffer to the routing net i'm designing a custom pillar via.
The mesh line that route the buffer driver to the buffer receiver could have different length and width.
Today, to ensure that the signal arrive to the buffer receiver, i'm choosing by default the largest buffer for the driver (BUFF_V20, BUFF_V16, BUFF_V24 ....)
My biggest fear is to have EMIR issues if the mesh line that route the driver to the receiver is a long line (hundreds of um of length for example) and a small width (1,2or3 um of width)
My questions are the following :
- Do you have any characterisation method, that allow me to choose the right buffer drive for both buffer driver and buffer receiver?
- I started a brainstorming to find some solutions and here what i did now;
- in an empty floorplan i place amnually the different buffer available in my library to implement the drivers. i made a choice of one buffer to use it as a receiver and place them aligned
with the drivers.
- i route manually the drivers to the receivers on METAL layer 3
- i generate a spef file to do an annotated simulation with spectre.
this implementation do not allow me to figure out which buffer i should use since the current and voltage are perfect with the different set of drivers. (no voltage drop or current attenuation during propagation)
I will be grateful to have your feedback and advices.