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Extract logic cells from design to match cells provided by pdk?

userOfTools

Hello,

I'm completely new to this so please bear with me.

If I'm provided with some standard cells, and would like to use a design that I have in an FPGA to port to an ASIC using the provided cells, how do I determine which of the provided cells I will need? Is there a way to get from the RTL or FPGA design the logic cells that I can use in an ASIC? The library I have with the standard cells has multiple logic cells for the same function (multiple nands, nors, etc.), so how would I know which ones my design will translate into?

Thanks!

  • Hi I would recommend running your rtl through a synthesis tool that can map your logic to the std cells in that PDK You can control this mapping. Do not allow 0 or 1x  size cells to be mapped, they will not drive a load...it maybe that your RTL is not in a standard format? Perhaps it was generated in MATLAB?  There may be a third party software app that can convert it but then you have to worry about the fidelity of the new file...Maybe my info is dated and MATLAB can now write out 'good' RTL....I have seen RTL generated by MATLAB and other similar tools that cannot be built i.e.  not possible to be physically manifested in FPGA or ASIC...There are many way to sanity check the RTL file.

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