• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. regarding digital flow

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 92
  • Views 13224
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

regarding digital flow

vijaysvk
vijaysvk over 5 years ago

Respected sir,

How can i design and simulate cmos inverter using digital flow and also ineed to do prelayout ans post layout for the same cmos inverter..can i use cadence encounter for this experiments

  • Cancel
Parents
  • Pinjare
    Pinjare over 5 years ago

    You can use virtuoso for designing and simulating a CMOS inverter. Encounter can be used for cell based design. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Pinjare
    Pinjare over 5 years ago

    You can use virtuoso for designing and simulating a CMOS inverter. Encounter can be used for cell based design. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information