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Verilog Code to Custom IC Layout generation

Hello everyone,

I am Vinay and I am currently developing some digital circuits for my chip design for my master's thesis at University at Buffalo.

I am fairly very new to Verilog and I don't seem to follow some of the things others find very easy.

Following are the things that I want to do to which I have no clue:

1. Develop certain arithmetic functionality in Verilog

2. Generate netlist for the verilog code

3. Feed the netlist file to Cadence encounter to be able to generate Digital Circuits' layout for my chip

I can use Cadence Virtuoso and Encounter for this but I don't know the exact procedure to get this done.

Could someone please describe the detailed process for doing the things mentioned above.

Thank you.

Parents

RTP MikeM over 5 years ago

Hello, It would likely be hard for you to follow the detailed flow without first gaining some knowledge on the higher overview. Start with understanding the flow by reviewing the video:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050wOEAQ&pageName=ArticleContent

Search for keywords like: Encounter RTL to GDSII then you will see links to more viewed recommendations.
Once you have the terminology and general flow, you can gain knowledge on the tools and development items by using Cadence Rapid Adoption Kits and video bytes.
You mentioned development of function in Verilog and Generate Netlist. Try the RC Adoption Kit.
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od00000066QHWEA2&pageName=ArticleContent

There are many online Verilog tutorials. Search through Cadence and Web to find items of development steps that you learned from the Encounter RTL to GDSII flow.
Best of luck on your quest and progress on your Thesis.
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RTP MikeM over 5 years ago

Hello, It would likely be hard for you to follow the detailed flow without first gaining some knowledge on the higher overview. Start with understanding the flow by reviewing the video:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050wOEAQ&pageName=ArticleContent

Search for keywords like: Encounter RTL to GDSII then you will see links to more viewed recommendations.
Once you have the terminology and general flow, you can gain knowledge on the tools and development items by using Cadence Rapid Adoption Kits and video bytes.
You mentioned development of function in Verilog and Generate Netlist. Try the RC Adoption Kit.
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od00000066QHWEA2&pageName=ArticleContent

There are many online Verilog tutorials. Search through Cadence and Web to find items of development steps that you learned from the Encounter RTL to GDSII flow.
Best of luck on your quest and progress on your Thesis.
Cancel
Vote Up +1 Vote Down

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vinayelk over 5 years ago in reply to RTP MikeM

Hi!

Good news! I already have my ASIC ready for tapeout. I defended my thesis all well! Back when I was posting this, I wasn't looking at things very right(didn't know Encounter was now Innovus and other stuff). But I have figured it out now

Thanks for all the help! I will definitely take a look at these videos to see if I can learn something more from them.
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