Cannot apply preserve attribute in VHDL source file

Hello,

we are currently synthesizing a design that contains some triple modular redundancy and we want to keep Genus from throwing out whats redundant. So we tried to set the "preserve" attribute in our VHDL file. Putting it on instances gave us errors because it could not be applied to unmapped instances. Applying it to the signals in question did not change anything.

Then my collegue put the "preserve" attribute on the exact same signals through the "set_dont_touch" command in Genus and it worked perfectly fine.

So I am a bit confused now. Is it just impossible to set attributes in the VHDL source file or am I doing something wrong? I also checked that the attributes are read in my FPGA tool which I use to test the code. Of course it does nothing with that attributes, it uses its own, but it still reads and displays them. So the syntax seems correct.

Thank you in advance for any help

Genus Version is 17.22