Regarding to LUP.6 Error in DRC for digital circuit P&R

Hello everyone 
Could you please help me to find out why this DRC.LUP.6 error appears in my layout design. ( kindly see the photo)

I am designing Read out circuit . 
RTL code implemented in verilog using Vivado design suite. 
I am using SoC Encounter- TSMC.180 nm for P&R , there is no any connectivity or geometry violations when I make verification in encounter. 
exporting the gds library to Vortuoso to check the DRC and LVS errors , then this error appears . 
please , help me to solve it. 

ERROR Description 

LUP.6 { @ Any point inside NMOS source/drain space to the nearest PW STRAP in the same PW <= 30 um
@ Any point inside PMOS source/drain space to the nearest NW STRAP in the same NW <= 30 um
@ In SRAM bit cell region, the rule is relaxed to 40 um
PACT_CHECK_NON_SRAM NOT NSTP_OS
PACT_CHECK_SRAM NOT (NSTP_OS OR NSTP_OS_SRAM)
NACT_CHECK_NON_SRAM NOT PSTP_OS
NACT_CHECK_SRAM NOT (PSTP_OS OR PSTP_OS_SRAM)
}