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Capacitor Array

JWMP

Hi,

I am trying to create a capacitor array in Innovus that is 8 cells in height and 32 cells in width. There is an issue once I read the Verilog netlist and place the design where the elements are completely randomly placed on the layout. An example is cell C0 (capacitor 0) has C129 (capacitor 129) stacked on top of each other. Ideally, I would like the left most of the design to start with an 8-cell stack from capacitors C0-C7. Then the next column would have capacitors C8-C15 and so on. Is there a way to ensure that the cells are placed in such a fashion?  

  • Hi,
    you can use the structured data path (SDP) functionality of Innovus to ensure the placement of the cells in the fashion you described.
    SDP allows the user to guide the place engine on how to place elements in a certain relation to each other. This approach is referred to as structured placement or relative placement.
    The SDP constraints are applied prior to placing the design, using either text commands or an SDP file with a dedicated format.

    Please refer to the Innovus user guide and Text command reference for more details on the commands and their usage.
    The user guide has a sample script for SDP placement that you can use as a starting point.

    Dimo

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