As of July 1, 2021, Google will discontinue the RSS-to-email subscriptions service.
Hence, the email alerts will be impacted while we explore other options. Please stay tuned for further communication from us.
For now we develop new project with number external hard macro devices (let's say it'll be few SPI modules, for simplification). Any of this external macro driven by generated clock in pretty similar frequency as main project. But main issue - we have analog-on-top flow and main digital pars is instantiated just as one of block in layout level.
I'm wandering is there some convenient method to manage timings/constraints for external macro (maybe some virtual macro connection). Basically we know exact timing relation for macros inputs/outputs and create it as library cell (with verilog, liberty and LEF) but obviously we cannot insert it to digital as it is not part of main digital part. Second problem - this macros will be moved and connection to them will be changed in different stages of layout so all the time we should need to recalculate input/output delay (with including numbers specified in liberty for macro).
In case there is exist some way to place this macro outside the boundary in innovus and count library numbers with some minor tuning of input/output delay - it would be great (without transfer this macros to layout).
Hi Nick, I am not sure I understood what you are trying to achieve.
You have an analog block on top, a digital block that will be instantiated in the analog, and hard macros, for which you have LEF and .lib files. Can you explain again where do you want to place the hard macros and why is this a problem ?Dimo
Yep, little bit confusing.
I have main digital part with different logic. And I have number of other different blocks as hard macro (SPI) which located somewhere in analog side. Unfortunately making just input/output constraints for connecting to this SPI blocks do not give me full STA analysis inside this blocks - basically they invisible for main digital.
And I'm asking if there some solution to virtually connect this macros to main part and just set net delays. As result I'll have fully covered timing analysing digital part with possibility of simulation, but when I'll import this modules, macro automatically cut and only main digital part stay for layout.
Macros in same way will be instantiated by layout engineers and they give me only capacitance/resistance for connecting nets (which I can apply to my full model and made re-implementation again any time)
Hi Nick, now I think I understand your question better. The SDC format does not have this concept of constraining your IOs with 'virtual blocks' connected to them. You can use SDC commands such as set_input_delay, set_output_delay, set_driving_cell, set_load etc. to create an abstract description of the outside world. However, you cannot use timing arcs of a cell/macro to serve as endpoints for timing paths leaving the design outputs. What you can do in this situation is run STA for the top implementation, and potentially use Tempus to write a timing ECO for fixes in the digital block.As your top level is implemented in analog, the best and most streamlined way would be to use the Mixed-Signal STA flow. For the MS-STA flow to work, you need to have OA flow setup, as opposed to the traditional LEF/DEF based flow. You can get some idea of how this flow looks like in the Mixed Signal Interoperability Guide. If you work with a DEF/LEF based flow, you will need to produce the data needed for the top level STA somehow - at least a netlist and top level constraints. Of course, the more data you provide to Tempus, the more accurate the timing analysis would be. If you have a DEF file that matches your netlist, you can run Quantus and do proper extraction for the interconnects. However, producing clean input data for Tempus from an analog block might be a not so straight-forward task and goes beyond my area of competence.
I think I get proper way to look at.