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[Innovus] create_generated_clock giving strange error TA-152

Nader Fathy

Hello,

I'm using Innovus (v21.11-s130_1) to do PnR for a simple instance of a clock divider synthesized by genus shown below:

module GENERATE_CTRL_CLOCKS #(parameter CLK_DIV_FACTOR = 5) (CLK_FAST,RST,CLK_SLOW);
  input CLK_FAST;
  input RST;
  output reg CLK_SLOW;
  // Counters & aux clocks
  reg [CLK_DIV_FACTOR-1:0] clk_counter;
  wire [CLK_DIV_FACTOR-1:0] clk_counter_incr;

  // Generate Clock Division
  always @ (posedge CLK_FAST or negedge RST) begin

    if (!RST)
      begin
        clk_counter <= {(CLK_DIV_FACTOR){1'b0}};
      end
    else
     begin
       clk_counter <= clk_counter_incr;
     end

  end

  assign clk_counter_incr = clk_counter + { {CLK_DIV_FACTOR-1{1'b0}}, 1'b1 };
  assign CLK_SLOW = ~clk_counter[CLK_DIV_FACTOR-1]; // Freq is CLK_DIV_FACTOR slower than fast clock
endmodule

module MAIN (CLK_FAST,RST);
  input CLK_FAST;
  input RST;
  wire CLK_SLOW;
  // Call clock div:
  GENERATE_CTRL_CLOCKS #(.CLK_DIV_FACTOR(5)) generate_ic_clocks(.CLK_FAST(CLK_FAST),.RST(RST), .CLK_SLOW(CLK_SLOW));
endmodule

My SDC to generate the clocks are defined as:

  • create_clock [get_ports CLK_FAST] -name clkf -period 48
  • create_generated_clock -name clks -source [get_ports CLK_FAST] -divide_by 32 [get_pins generate_ic_clocks/CLK_SLOW_reg/Q]
Innovus gave me these errors when I do placeDesign:
  • **ERROR: (TA-152): A latency path from the 'Rise' edge of the master clock  at source pin 'CLK_FAST' to the 'Rise' edge of generated clock 'clks' at pin 'generate_ic_clocks/CLK_SLOW_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clks'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
  • **ERROR: (TA-152): A latency path from the 'Rise' edge of the master clock  at source pin 'CLK_FAST' to the 'Fall' edge of generated clock 'clks' at pin 'generate_ic_clocks/CLK_SLOW_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'clks'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false

I have viewed the article (https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nUuREAU&pageName=ArticleContent) that talks about this issue but my clocks don't have any of the mentioned issue.

If I flattened the module GENERATE_CTRL_CLOCKS on the main module and modified the path of SDC SLOW_CLK to [get_pins I_1/Z] which points to the output of CLK_SLOW in schematics view, Innovus recognizes the slow clock.

I'd appreciate it if anyone could help me understand why is this happening? and how do I fix this issue, please?

Nader Fathy

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