Understanding the exact definition of capacitances reported in the stdcells.report by Voltus in order to reuse for making power-domain decoupling models for EMC simulations

Introduction: Task at Hand

• Determine resonance frequencies of a chip + package model. Package model is available, models need to be created for the impedance introduced by power domains between the supplies.
• The chip is a large mixed-signal system in a 40 nm process with multiple power domains.
• Voltus has been used to generate PowerGrid Views. The tool can be used to generate reports for the library cells and in particular the "stdcells.report" which lists capacitance values extracted from simulations at cell level.
• Statistics are available about the number of cells used per domain, about supply rail lengths, etc.
• The intention is to compute totals of capacitances per domain, and deduce an average capacitance density per unit length of rail (as well as an associated series resistance to have correct rise-times). Then evaluate rails parasitics (series resistance and inductance, substrate resistance) and construct a distributed model using the averaged parameters for each domain.

Problem Description

• So far no precise definition was found in the various Voltus manuals for the capacitance values reported in the "stdcells.report".
• What is "grid capacitance" exactly ?
• What is "intrinsic capacitance" exactly ?

Questions

1. How can I determine what the precise definition is of the capacitances reported in the "stdcells.report" generated from the PG views ?
   Is there a way to look at the nelists used for extraction ?
   
   
2. It appears the "stdcells.report" lists one capacitance value per supply pin:  is this a capacitance computed with all other supply pins "AC grounded" or equivalently driven by a perfect voltage source ?
   
   
3. The capacitance values in the "stdcells.report" are independent of the logic level imposed on the inputs. However the capacitances to any supply from a given cell will depend how an external driver ties a particular input of the cell to any of those supplies...  So what is then the value reported in the  "stdcells.report" ? Is is assuming some distribution of logic levels at the inputs (eg assuming all possible combinations have the same probability) ?

Looking forward for hints on how find answers to these questions (or even better direct answers if possible) !