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How to read a NDL netlist ?which tool generates NDL netlist?how to read a EDIF netlist?which tool generates EDIF netlist?

I see read_design command in conformal lec supports NDL,EDIF netlist.I dont see any tool which generates this kindof formats.How to read those files as a schematic?Which tool generates these netlist?How to convert those netlist to verilog or vhdl format?

Thanks,

Arun

Arunpandiyan Anbarasu over 2 years ago

Can anyone please respond to this query?I couldnt get any details on this.
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DimoM over 2 years ago in reply to Arunpandiyan Anbarasu

Hi,

I am not a Conformal expert and did not even hear about these formats before reading your query. However, looking at the read_design command documentation, it seems to me these are just two out of a number of supported formats, along with other better known options such as VHDL, Verilog and SystemVerilog.

-Dimo
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Arunpandiyan Anbarasu over 2 years ago in reply to DimoM

I agree to your point,But I want to know detail about these two formats.
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DimoM over 2 years ago in reply to Arunpandiyan Anbarasu

These are not Cadence tool-specific formats.
I suggest you to find some documentation and literature via Google search.

- Dimo
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Arunpandiyan Anbarasu over 2 years ago in reply to DimoM

I couldnt able to find details on NDL in google search.
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Arunpandiyan Anbarasu over 2 years ago in reply to Arunpandiyan Anbarasu

I found some links on the google.If it is copyrighted links,please feel free to delete it from the post.

https://github.com/sumanishs/boost-edif-parser/blob/master/fibex_example.edif ----------->edif file

https://www.freepatentsonline.com/5644498.html ----->Lsi file (NDL file)

https://semiengineering.com/entities/lsi-logic/

https://archive.org/details/lsilogicdatabook00texa/mode/2up

http://www-lab09.kuee.kyoto-u.ac.jp/parthenon/NTT/hajimete_e/4shou.htm --------->NDL file

I tried reading NDL file and EDIF file of full adder by using read_design command.It worked properly in Conformal LEC.But Since I dont have proper library for EDIF and NDL,I couldnt make the design equivalent.

It will be better if there is small testcase provided to explain EDIF and NDL comparison in LEC.

Thanks,

Arun
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