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Community Forums Digital Implementation PG nets are not routed with sroute

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PG nets are not routed with sroute

HarryDD
HarryDD 2 months ago

Hello,

I have a netlist with PG nets named VDD and VSS and furthermore a def with I/O pins and PG ports and nets. In the def the PG nets are named VDD09V and VSS09V.

What I did is the following for power routing:

connect_global_net VDD0V9 -pin_base_name VDD -type pg_pin -all -verbose -override
connect_global_net VSS0V9 -pin_base_name VSS -type pg_pin -all -verbose -override

The output is 

8195 new pwr-pin connections were made to global net 'VDD0V9'.
8195 new gnd-pin connections were made to global net 'VSS0V9'.

So far so good - I hope.

Then, I am adding my stripes connecting to the PG ports from the def:

add_stripes -nets {VSS0V9} -layer 7 \
-direction vertical \
-width 2.5 -spacing 5 -number_of_sets 30 \
-extend_to design_boundary -create_pins 1 \
-start_from left \
-start_offset 10 -stop_offset 4

add_stripes -nets {VDD0V9} -layer 7 \
-direction vertical \
-width 2.5 -spacing 5 -number_of_sets 29 \
-extend_to design_boundary -create_pins 1 \
-start_from left \
-start_offset 15 -stop_offset 9

Also this seems to work perfectly.

After this, I am setting up sroute:

set_db route_special_via_connect_to_shape {stripe followpin}  ==> my expectation here is to connect the PG pins using followpin and connecting this M2 horizontal layer to my M7 vertical power stripes with vias

However, when runnng sroute then with

route_special -connect {core_pin} \
-core_pin_target {stripe} \
-detailed_log \
-nets { VSS0V9D VDD0V9D } -stripe_layer_range { M2 M7 }

no M2 followpin lines are generated (and therefore no via connection can be made):

Begin option processing ...
srouteConnectPowerBump set to false
routeSelectNet set to "VSS0V9D VDD0V9D"
routeSpecial set to true
srouteConnectBlockPin set to false
srouteConnectConverterPin set to false
srouteConnectPadPin set to false
srouteConnectStripe set to false
srouteCorePinTarget set to "stripe"
srouteDetailedLog set to true
srouteFollowCorePinEnd set to 3
srouteFollowPadPin set to false
srouteJogControl set to "preferWithChanges differentLayer"
srouteMaxStripeLayer set to 7
srouteMinStripeLayer set to 2
srouteNoViaOnWireShape set to "padring ring blockring blockpin coverpin noshape blockwire corewire iowire"
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 2791.00 megs.

Reading DB technology information...
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
**WARN: (IMPSR-4302): Cap-table/qrcTechFile is found in the design, so the same information from the technology file will be ignored.
Read in 19 layers, 9 routing layers, 1 overlap layer
Read in 2 nondefault rules, 0 used
Read in 1685 macros, 424 used
Read in 409 components
409 core components: 409 unplaced, 0 placed, 0 fixed
Read in 332 physical pins
332 physical pins: 0 unplaced, 0 placed, 332 fixed
Read in 2 logical pins
Read in 208 nets
Read in 4 special nets, 2 routed
Read in 1150 terminals
2 nets selected.

Begin power routing ...
Total Ports:
Total CPU time for maze routing 0 seconds
Number of Core ports routed: 0
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 2822.00 megs.

Begin updating DB with routing results ...
Updating DB with 332 io pins ...
Updating DB with 0 via definition ...
route_special created 0 wire.
ViaGen created 0 via, deleted 0 via to avoid violation.

I am using Innovus 20.13

Any hint what I am doing wrong / what I am missing?

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  • DimoM
    DimoM 2 months ago

    Hi Harry,

    I see you have 4 power net in two sets "VDD0V9  VSS0V9"  and " VSS0V9D VDD0V9D".  sroute is hinting at that with this message Read in 4 special nets, 2 routed


    You will have to review your PG intent. Do you want to connect your followpins to VSS0V9D VDD0V9D ? You used the other set in connect_global_net command.

    - Dimo

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  • HarryDD
    HarryDD 2 months ago in reply to DimoM

    Hi Dimo,

    thanks for your reply. No, there is only VSS/VDD from the standard cells itself and VSS0V9D VDD0V9D from the def I received. Don't know where the "D" from the other VDD0V9 VSS0V9 have been lost.

    But you may right, the power intent could be a problem. I also have a upf file where only VSS VDD is mentioned. So I guess, first the upf and the def file have to be aligned to get the correct power intent.

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  • HarryDD
    HarryDD 2 months ago in reply to HarryDD

    Indeed, this was solved simply with a correct upf!

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