Stats

  • Locked Locked
  • Replies 5
  • Subscribers 92
  • Views 4493
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Doing synthesis with a composed cell in netlist [GENUS][Verilog]

Johanny Saenz

Hi.

I want to synthesize a digital block prioritizing a custom Verilog netlist made of standard cells. I have created the following module as AOI.v file:

module AOI(a, b, c, d, y);
input a,b,c,d;
output y;
wire n_0,n_1;
AN2 g1(.A1(a),.A2(b),.O(n_0));
AN2 g2(.A1(a),.A2(b),.O(n_1));
OR2 g3(.A1(n_0),.A2(b),.O(y));
endmodule

The module AOI is composed of standard cells. The idea is to map my circuit taking into account that block (it has advantages to my application)
I have no timing arcs of that block. The synthesis should take them from STD cell liberty file.
How can I pass it to GENUS?
Thanks

  • Hi Johanny,
    I assume the cells AN2 and OR2 are standard cells from the library. In this case you don't have to do much, just instantiate your module AOI where you need it in your RTL.
    You will see the standard cells in the netlist already after elaboration.

    You will have to set the preserve attribute on the instances to prevent them from being modified during synthesis. Or set the preserve directly on the sub-design AOI, this should also work.

    -Dimo

  • in reply to DimoM

    Hi Dimo.

    I want to take into account the logic of my module AOI during the mapping and optimizations. My synthesis should decide wherever to place the module AOI inside my design. 

    Is there a way to include it?

  • in reply to Johanny Saenz

    Hi Johanny,
    I am not aware of a way of doing that. Genus will try to find a combination of cells such that it produces the smallest design meeting the timing requirements of the block. Even if it is possible to give this module as a target block for synthesis, Genus will not use it if it sees a better (read: smaller) combination of cells.

    What is exactly that you are trying to achieve here, what is the advantage that you expect to see ?

  • in reply to DimoM

    Dimo.

    Simplifying the problem:

    I want to replace a specific standard cell with a module that contains standard cells.  Why? Because I'm ensuring some redundancy on that module to prevent failure.

    Hint: Standard cell and module have the same logic equivalence. For instance, triplicate logic but same functional behavior.

    Steps to be followed:

    - Mapping + Opt

    - Substitution

    - Running again a time analysis and optimization with preservation.

  • in reply to Johanny Saenz

    I see. I would recommend taking a look at the following articles:
    Triple Voting Flop (TVF) Insertion - A script-based solution for adding voting/redundancy logic. Maybe you can reuse something from here.

    The following rapid adoption kit presents the unified safety format:
    RAK: Safety Implementation & Verification with Unified Safety Format (USF)
    I have not used any of this functionality, and some of it will probably require extra licenses, but if you need safety features it is worth taking a look.

    -Dimo

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.