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Questions about a constraint in the SDC

Goddard

I encounter the following command while reading the SDC:

  • create_generate_clock [list [get_pins pciex4_2_clk] [get_pins pciex4_2_clk_clks]] -name pciex4_2 -source [get_port xx ] -dvide_by 1

Now I know this constraint can be enforced, but I wonder when such a constraint is necessary?

By the way, I'd like to consult the difference between [get_ports] and [get_pins] when create_generated_clock?

Thanks a lot if anyone could anwser my questions.

Parents

  • Hi,
    these questions are very basic and are covered in any good book on static timing analysis.
    I can recommend "Static Timing Analysis for Nanometer Designs" by Rakesh Chadha and J. Bhasker

    Also you can search through support.cadence.com for some short videos and tutorials on STA.

    Furthermore you can search for each command in the support page and you will find some explanation of what it is doing.

    -Dimo

  • in reply to DimoM

    Dear Dimo,

    Thanks for your replay, I  read the SDC section of "Static Timing Analysis for Nanometer Designs" but didnt find such command,mabye I didnt make it clear. I dont know why generate the same clock on two different pins and what is the purpose of doing so? 

    Maybe this question is also very basic. Since I am a newcomer, I hope you can understand if I ask any stupid questions. Thanks a lot.

  • in reply to Goddard

    Hi,
    you are of course very welcome to ask questions, that is what this forum is for. I just did not see any added value in copying and pasting information from the documentation about each command.

    Now to the question of why the generated clock is defined on two pins at once:
    There might be various reasons for that. One example that comes to mind are two clock gating cells in parallel, being controlled with the same enable signal. In this case the designer might want to have the fanout of both of them see the same generated clock, so the generated clock needs to be defined on the output of both clock gating cells. 

    Of course, this is just a synthetic example. In a real-world design there is more than one way to describe the timing intent, and it is up to the designer to decide on how to do the constraining in the most effective way.

    -Dimo

Reply
  • in reply to Goddard

    Hi,
    you are of course very welcome to ask questions, that is what this forum is for. I just did not see any added value in copying and pasting information from the documentation about each command.

    Now to the question of why the generated clock is defined on two pins at once:
    There might be various reasons for that. One example that comes to mind are two clock gating cells in parallel, being controlled with the same enable signal. In this case the designer might want to have the fanout of both of them see the same generated clock, so the generated clock needs to be defined on the output of both clock gating cells. 

    Of course, this is just a synthetic example. In a real-world design there is more than one way to describe the timing intent, and it is up to the designer to decide on how to do the constraining in the most effective way.

    -Dimo

Children
  • in reply to DimoM

    Dear Dimo,

    Thanks for your prompt reply. The reason why I was confused before was that I thought the name of each clock was unique, which made me think that the clock name corresponded to the clock one by one. Now you have given me this actual case, which makes me understand more possibilities of clock constraint,and I will further study SDC.

    Thanks again.

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