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Questions about a constraint in the SDC

Goddard

I encounter the following command while reading the SDC:

  • create_generate_clock [list [get_pins pciex4_2_clk] [get_pins pciex4_2_clk_clks]] -name pciex4_2 -source [get_port xx ] -dvide_by 1

Now I know this constraint can be enforced, but I wonder when such a constraint is necessary?

By the way, I'd like to consult the difference between [get_ports] and [get_pins] when create_generated_clock?

Thanks a lot if anyone could anwser my questions.

Parents

  • The create_generated_clock command you provided is used in digital design to create a clock signal based on an existing clock. This can be necessary in several cases, such as when different parts of a design require different clock frequencies, or when a clock signal needs to be distributed across multiple clock domains.

    In this specific example, the command is creating a new clock signal named "pciex4_2" based on the clock signal sourced from the port "xx" and divided by a factor of 1. The get_pins command is used to identify the source clock pins, which are associated with the existing clock signal, while get_port is used to identify the clock port associated with the new clock signal.

Reply

  • The create_generated_clock command you provided is used in digital design to create a clock signal based on an existing clock. This can be necessary in several cases, such as when different parts of a design require different clock frequencies, or when a clock signal needs to be distributed across multiple clock domains.

    In this specific example, the command is creating a new clock signal named "pciex4_2" based on the clock signal sourced from the port "xx" and divided by a factor of 1. The get_pins command is used to identify the source clock pins, which are associated with the existing clock signal, while get_port is used to identify the clock port associated with the new clock signal.

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