Genus standard cells to module

Hi, I have a TCL script for synthesizing a full adder (see below).

I am trying to modify the script so that when Genus opens, the schematic represents the circuit in module form.

I don't want to see the standard cell circuits and would like to see something simple. It seems I have gotten this to happen but I am not sure how.

When I source the script below, Genus opens and I get the first schematic (schematics are shown below). Without closing Genus, I source the script again and get the second schematic (preferred one).

What is happening that is causing the schematic to change when I source the script for a second time? How I can set the script such that the second schematic is by default? Thanks!

#### Include TCL utility scripts..
include load_etc.tcl
#### Set up
set DESIGN fulladder
set SYN_EFF medium
set MAP_EFF medium
set DATE [exec date +%m%d.%H%M]
set map_fancy_names 1
set iopt_stats 1

set SYN_PATH "."
set_db lib_search_path /home/transistor
set_db init_hdl_search_path .
set_db information_level 7
set_db library {transistor.lib}
set_db hdl_array_naming_style %s\[%d\]

set_db tns_opto true

read_hdl ./inputs/dig.v

elaborate $DESIGN

puts "Runtime & Memory after 'read_hdl'"
timestat Elaboration

check_design -unresolved

report timing -lint -verbose

#### Synthesizing to generic
set_db syn_generic_effort $SYN_EFF
puts "Runtime & Memory after 'synthesize -to_generic'"
timestat GENERIC
set_db auto_ungroup none
syn_generic

#### Synthesizing to gates
set_db syn_map_effort $MAP_EFF
puts "Runtime & Memory after 'synthesize -to_map -no_incr'"
timestat MAPPED

syn_map

remove_assigns_without_optimization
set_db syn_map_effort $MAP_EFF
insert_tiehilo_cells
puts "Runtime & Memory after incremental synthesis"
timestat INCREMENTAL

syn_opt

report area > ./outputs/${DESIGN}_area.rpt
report gates > ./outputs/${DESIGN}_gates.rpt
write_hdl > ./outputs/${DESIGN}.vg
write_sdc > ./outputs/${DESIGN}.sdc

gui_show;

1st Schematic 

2nd schematic (preferred)