DRC Violations on Auto-generated layout using Innovus

First of all, yes, the tool knows the design rules based on the technology LEF file.

In General: nano route tries to find connections that do not violate design rules. If it is unable to do so, it prefers creating traces that are either short cuts or DRC violations rather than leaving the port unconnected. In other words, no, Innovus is not necessarely able to generate a DRC-clean layout in all cases.

DRC violations can be fiexed to some extent in the post-route optimization. The Innovus User Guide provides some help here.

Now to your case. I do not see any shortcuts on the layout. Since all VDD connections of your standard cells are marked as shortcuts, I assume that you forgot to assign the power and ground pins of your standard cells to the global power/ground net. This is done with the globalNetConnect command. You can study that command in the Innovus Text Command Reference to get more information.

Hope that helps.

First of all, yes, the tool knows the design rules based on the technology LEF file.

In General: nano route tries to find connections that do not violate design rules. If it is unable to do so, it prefers creating traces that are either short cuts or DRC violations rather than leaving the port unconnected. In other words, no, Innovus is not necessarely able to generate a DRC-clean layout in all cases.

DRC violations can be fiexed to some extent in the post-route optimization. The Innovus User Guide provides some help here.

Now to your case. I do not see any shortcuts on the layout. Since all VDD connections of your standard cells are marked as shortcuts, I assume that you forgot to assign the power and ground pins of your standard cells to the global power/ground net. This is done with the globalNetConnect command. You can study that command in the Innovus Text Command Reference to get more information.

Hope that helps.

Hello Domi,

Thank you very much for your reply! Very helpful! 

I have double-checked the assignments of power pins, and it seems I already have it in my tcl file. Please find my source tcl file in the attachments. 

I am not quite sure about the order of the commands in the tcl file. I hope it is as it should be. It is my first time using Innovus. I would be very grateful if you can have a look at the file and let me know if I have something wrong or missing. 

Many thanks,

Anas

########

setMultiCpuUsage -localCpu max

set module chip

set_global _enable_mmmc_by_default_flow $CTE::mmmc_default
suppressMessage ENCEXT-2799

getDrawView
loadWorkspace -name Physical

set ::TimeLib::tsgMarkCellLatchConstructFlag 1
set _timing_save_restore_compression_mode hybrid
set degHonorSignalNetNDR 1
set defHierChar /
set delaycal_input_transition_delay 0.1ps
set distributed_client_message_echo 1
set distributed_mmmc_disable_reports_auto_redirection 0
set fpIsMaxIoHeight 5
set gpsPrivate::dpgNewAddBufsDBUpdate 1
set gpsPrivate::lsgEnableNewDbApilnRestruct 1
set init_gnd_net {VSS}
set init_pwr_net {VDD}

## change the folowing file
set init_io_file padframe.io


## change the folowing file
set init_lef_file {/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tcb018gbwp7t_270a/lef/tcb018gbwp7t_5lm.lef /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tpd018bcdnv5_160a/mt/5lm/lef/tpd018bcdnv5_5lm.lef}



## change the folowing file
set init_mmmc_file viewDefinition_chip.tcl

set init_oa_search_lib {}


## change the folowing file
set init_verilog chip_m.v



set latch_time_borrow_mode max_borrow
set 1sg0CPGainMult 1.390000
set pegDefaultResScaleFactor 1.900000
set pegDetailResScaleFactor 1.990000
set report_inactive_arcs_format {from to when arc_type sense reason}
set timing_library_float_precision_tol 0.900010
set timing_library_load_pin_cap_indices {}
set timing_library_write_library_to_directory {}
set tso_post_client_restore_command {update_timing ; write_eco_opt_db ;}

setDesignMode -process 180

init_design


floorPlan -noSnapToGrid -d 4260 4260 100 100 100 100
setFPlanRowSpacingAndType 50 1

#addIoFiller -cell PFILLER05 -prefix FILLER -side n
#addIoFiller -cell PFILLER05 -prefix FILLER -side e
#addIoFiller -cell PFILLER05 -prefix FILLER -side w
#addIoFiller -cell PFILLER05 -prefix FILLER -side s


globalNetConnect VDD -type pgpin -pin VDD -override -verbose -netlistOverride
globalNetConnect VSS -type pgpin -pin VSS -override -verbose -netlistOverride


### Pin Placement
setPinAssignMode -pinEditInBatch true

editPin -side W -layer M3 -fixedPin 1 -spreadType center -spacing 80 -pin {VSS[2] clk IN_Valid Ker_Read In_ker[0] In_ker[1] In_ker[2] In_ker[3] In_ker[4] In_ker[5] In_ker[6] In_ker[7] In_ker[8] In_ker[9] In_ker[10] In_ker[11] In_ker[12] In_ker[13] In_ker[14] In_ker[15] In_ker[16] In_ker[17] VDD[1] VSS[1] In_sig[0] In_sig[1] In_sig[2] In_sig[3] In_sig[4] In_sig[5] In_sig[6] In_sig[7] In_sig[8] In_sig[9] In_sig[10] In_sig[11] In_sig[12] In_sig[13] In_sig[14] In_sig[15] In_sig[16] In_sig[17] Sig_Read MAC reset VDD[0]}

editPin -side N -layer M3 -fixedPin 1 -spreadType center -spacing 80 -pin {VDD[2] Con_out[0] Con_out[1] Con_out[2] Con_out[3] Con_out[4] Con_out[5] Con_out[6] Con_out[7] Con_out[8] Con_out[9] Con_out[10] Con_out[11] Con_out[12] Con_out[13] Con_out[14] Con_out[15] Con_out[16] Con_out[17] Con_Valid VSS[3] VDD[3] Max[0] Max[1] Max[2] Max[3] Max[4] Max[5] Max[6] Max[7] Max[8] Max[9] Max[10] Max[11] Max[12] Max[13] Max[14] Max[15] Max[16] Max[17] VSS[4]}

editPin -side E -layer M3 -fixedPin 1 -spreadType center -spacing 80 -pin {VSS[6] Ker_index[0] Ker_index[1] Ker_index[2] Ker_index[3] Ker_index[4] Ker_index[5] Time_shift[0] Time_shift[1] Time_shift[2] Time_shift[3] Time_shift[4] Time_shift[5] Time_shift[6] Time_shift[7] Time_shift[8] Time_shift[9] Time_shift[10] Time_shift[11] code_new VDD[5] VSS[5] chann_no[0] chann_no[1] chann_no[2] chann_no[3] chann_no[4] chann_no[5] chann_no[6] chann_no[7] new_spi mul_out[0] mul_out[1] mul_out[2] mul_out[3] mul_out[4] mul_out[5] mul_out[6] mul_out[7] mul_out[8] mul_out[9] mul_out[10] mul_out[11] mul_out[12] mul_out[13] mul_out[14] mul_out[15] mul_out[16] mul_out[17] mul_Valid VDD[4]}

editPin -side S -layer M3 -fixedPin 1 -spreadType center -spacing 80 -pin {VDD[6] shi_out[0] shi_out[1] shi_out[2] shi_out[3] shi_out[4] shi_out[5] shi_out[6] shi_out[7] shi_out[8] shi_out[9] shi_out[10] shi_out[11] shi_out[12] shi_out[13] shi_out[14] shi_out[15] shi_out[16] shi_out[17] shi_Valid Ker_full_read shift_notify VSS[7] VDD[7] sub_out[0] sub_out[1] sub_out[2] sub_out[3] sub_out[4] sub_out[5] sub_out[6] sub_out[7] sub_out[8] sub_out[9] sub_out[10] sub_out[11] sub_out[12] sub_out[13] sub_out[14] sub_out[15] sub_out[16] sub_out[17] sub_Valid FB_unit_finish VSS[0] }

setPinAssignMode -pinEditInBatch false


addRing -skip_via_on_wire_shape Noshape -exclude_selected 1 -skip_via_on_pin Standardcell -center 1 -stacked_via_top_layer M3 -type core_rings -jog_distance 0.56 -threshold 0.56 -nets {VDD VSS} -follow core -stacked_via_bottom_layer M3 -layer {bottom M3 top M3 right M4 left M4} -width 6 -spacing 2 -offset 2


sroute -connect { blockPin corePin padPin padRing floatingStripe } -layerChangeRange { M1 M5 } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -padPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -floatingStripeTarget { blockring padring stripe ringpin blockpin followpin } -allowJogging 1 -crossoverViaLayerRange { M1 M5 } -nets { VDD VSS } -allowLayerChange 1 -blockPin useLef -targetViaLayerRange { M1 M5 }


setPlaceMode -placeIOPins 1
placeDesign -noPrePlaceOpt




## to add spare cells
#createSpaareModule -moduleName my_spare -cell {cell1 cell2 ,..}

#addFiller -cell feedth9 -prefix FILLER-doDRC
#addFiller -cell feedth3 -prefix FILLER-doDRC
#addFiller -cell feedth -prefix FILLER-doDRC


## report timing after placment
#report_timing -unconstrained -delay_limit 1 > reports/$module/timing_report_postPlace.prt

## change the folowing file
#clockDesign -specFile Clock.ctstch -outDir clock_report -fixedInstBeforeCTS

set_ccopt_property target_max_trans 0.294
set_ccopt_property target_skew 1

setCTSMode -engine ccopt


#create_ccopt_clock_tree -name clk_200M -source clk_200M
#ccopt_design

## report clock trees and skew groups
#report_ccopt_clock_trees -file reports/$module/clock_trees.rpt
#report_ccopt_skew_groups -file reports/$module/skew_groups.rpt


## report timing after CTS
#report_timing -unconstrained -delay_limit 1 > reports/$module/timing_report_postCCopt.prt


setOptMode -fixCap true -fixTran true -fixFanoutLoad false
optDesign -preCTS
optDesign -postCTS



routeDesign -globalDetail



## report drc and connectivity
#verify_drc -report reports/$module/DRC.drc
#verify_connectivity -report reports/$module/CONNECTIVITY.connect



setAnalysisMode -analysisType onChipVariation -cppr both

setOptMode -fixCap true -fixTran true -fixFanoutLoad false
optDesign -postRoute


saveDesign myDesign

#set map_file /home/mchiama6/mapping_file
#streamOut results/$module/GDS.gds -mapFile $map_file -libName tcb018gbwp7t_5lm -units 2000 -mode ALL


## extracting rc
#setExtractRCMode -effortLevel high -qrcOutputMode rcdb -engine postRoute
#extractRC
#reOut -spef SPEF/QRC_x_file.spef

## for sign off extraction
#setExtractRCMode -effortLevel high -qrcOutputMode rcdb -engine postRoute -lefTechFileMap ******


### generating qrc_tech_file
## Techgen -techinfo qrcTechFile

The commands

innovus > globalNetConnect VDD -type pgpin -pin VDD -override -verbose -netlistOverride

innovus > globalNetConnect VSS -type pgpin -pin VSS -override -verbose -netlistOverride

are only correct if "VDD" and "VSS" are the actual names of the power nets in your standard cells. Can you doublecheck whether that is the case? You can do that by investigating the LEF file of your standard cell library. Furthermore, I don't think you need the -override and -netlistOverride commands here.

Here is a minimum example:

Suppose that the name of the power and ground net of our standard cells are "VDD" and "GND". Moreover, we would like to call the global power and ground net in our digital design "Vddd" and "Vssd". The correct syntax would then be

innovus > set init_pwr_net {Vddd}

innovus > set init_gnd_net {Vssd}

innovus > <other init commands>

innovus > init_design

innovus > globalNetConnect Vddd -type pgpin -pin VDD -all

innovus > globalNetConnect Vssd -type pgpin -pin GND -all

The additional argument -all ensures that the global net connection is applied to all instances in the design (as long as you do not have multiple power domains with overlapping names this argument is safe to use).

Hope that helps.

Dear Domi, 

Thanks for your reply! 

It seems VDD and VSS are actually the correct terms used in the standard cells. Please see the image below - not sure about "use ground & use power".

Thank you very much for your time!

Anas

If these entries are inside the macro of a standard cell then yes, VDD and VSS are correct. The use ground and use power tell the tool that these are special pins that will be routed with the sroute command, so that's is correct.

Just to be sure (because I wouldn't know what else causes this error) try running the following mini TCL script:

set lib_ground [lindex [dbGet [lindex [dbGet -p head.libCells.baseClass core] 0].pgTerms.name] 1]
set lib_power  [lindex [dbGet [lindex [dbGet -p head.libCells.baseClass core] 0].pgTerms.name] 0]
puts $lib_ground
puts $lib_power

The output of that script tell you the names of the power and ground net(s).

Thanks, Domi! 

This is the output of the provided commands: 

It seems the power and ground nets are fine. 

I will try to export the design as GDS file and verify it on Virtuoso (using Calibre). I'm not currently quite sure how to do this - but this is beyond the purpose of this post, I have created another post if you would like to contribute to it (that would be great!). 

Please let me know if you have any other thoughts on how this could be tackled. 

Many thanks,

Anas

Did you notice that power and ground are mixed up? power should be VDD and ground should be VSS. (might just be an indexing issue, not necessarely an error)

I didn't actually notice it !! hahaha!
Yes, I think it is the order it was saved/read out probably. 

Thank you, Domi!

About the design export:

First of all, the DRC check of Innovus is - to my experience - reliable, meaning that if Innovus reports DRC violations than the DRC check in Virtuoso will show them too. I don't know too much about the design flow where a digital design is converted into a layout, but I think all you need is the oaOut command. The syntax is

Innovus > oaOut <name_of_your_library> <name_of_your_design> <cell_view_type>

The cell view type is "layout". Furthermore, you might need the optional -leafViewNames and the -reLibs arguments. So an example call could look like this

Innovus > oaOut myLib myDesign layout -leafViewNames {layout} -refLibs {myStandardCellLibrary}

This will generate a Layout view in the cell "myDesign" inside the library "myLib". In order to perform a LVS check, you also need a schematic and, in case you want to simulate your design, a functional view. Both can be done in Vortuoso by selecting File -> Import -> Verilog. There you select your gate-level netlist.

Hope that helps.

Side note: You might also need to specify a gds map file at some point. The gds format has predefined layer purposes, i.e. layer 1 has a specific purpose, layer 2 has one, and so on. The mapping between the layers of your process and the gds format is done with said map file (a .map file), which should be located somewhere in your installation directory.