Innovus/Encounter: Power pins are not connected to power rings

Hi Anas,
you log dump is not human readable.
You will have to divide and conquer the problem.

The sRoute commands, according to the tool command reference:
"Routes power structures. Use this command after creating power rings and power stripes. Depending on the parameters you use, it can do any or all of the following:
  Create pad rings
  Connect pins on specified nets on the blocks
  Connect pads to nearby rings or stripes
  Extend unconnected stripes to make a connection
  Route standard cell pins"

I suggest you to work with separate runs for the separate tasks. After creating the rings try to create th command that connects the rings to the pads. If it does not work, check for warning and error messages, and try to understand what the tool tries to tell you.

- Dimo

Hi Dimo, 

Thanks for your reply. 

Sorry, for some reason, I could not upload the log file. I just had to copy it here. 

After adding the power ring, I tried connecting only the VSS net using Route -> Spacial route from the user interface. The log I have for this command is as follows: 

*** Begin SPECIAL ROUTE on Tue Mar 21 15:52:21 2023 ***
SPECIAL ROUTE ran on directory: /home/mchiama6/spiketrum
SPECIAL ROUTE ran on machine: allman (Linux 3.10.0-1160.76.1.el7.x86_64 Xeon 2.93Ghz)

Begin option processing ...
srouteConnectPowerBump set to false
routeSelectNet set to "VSS"
routeSpecial set to true
srouteBlockPin set to "useLef"
srouteBottomLayerLimit set to 1
srouteBottomTargetLayerLimit set to 1
srouteConnectConverterPin set to false
srouteCrossoverViaBottomLayer set to 1
srouteCrossoverViaTopLayer set to 5
srouteFloatingStripeTarget set to "blockring padring ring stripe ringpin blockpin foll owpin"
srouteFollowCorePinEnd set to 3
srouteJogControl set to "preferWithChanges differentLayer"
srouteNoViaOnWireShape set to "padring ring stripe blockring blockpin coverpin blockwi re corewire followpin iowire"
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
srouteStopBlockPin set to "nearestTarget"
srouteTopLayerLimit set to 5
srouteTopTargetLayerLimit set to 5
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 3999.00 megs.

Reading DB technology information...
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
Read in 11 layers, 5 routing layers, 1 overlap layer
Read in 570 macros, 83 used
Read in 277 components
81 core components: 81 unplaced, 0 placed, 0 fixed
196 pad components: 0 unplaced, 0 placed, 196 fixed
Read in 182 physical pins
182 physical pins: 0 unplaced, 0 placed, 182 fixed
Read in 182 nets
Read in 2 special nets, 2 routed
Read in 263 terminals
1 net selected.

Begin power routing ...
**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of t he VSS net were not found in the design. Check netlist or change the parameter value t o include block pins in the design.
**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the VSS net due to un availability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.
Type 'man IMPSR-1256' for more detail.
Cannot find any AREAIO class pad pin of net VSS. Check net list, or change port class in the technology file, or change option to include pin in given range.
CPU time for VSS FollowPin 0 seconds
Number of IO ports routed: 0
Number of Block ports routed: 0
Number of Stripe ports routed: 0
Number of Core ports routed: 0
Number of Pad ports routed: 0
Number of Power Bump ports routed: 0
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 4001.00 megs.

Begin updating DB with routing results ...
Updating DB with 182 io pins ...
Updating DB with 0 via definition ...
sroute created 0 wire.
ViaGen created 0 via, deleted 0 via to avoid violation.

I'm not sure where to start from, the netlist is generated using Genus from a VHDL RTL code. In my RTL design, I have VDD and VSS inout pins. 

Thanks for you help. 

Anas

Hi Dimo, 

Thanks for your reply. 

Sorry, for some reason, I could not upload the log file. I just had to copy it here. 

After adding the power ring, I tried connecting only the VSS net using Route -> Spacial route from the user interface. The log I have for this command is as follows: 

*** Begin SPECIAL ROUTE on Tue Mar 21 15:52:21 2023 ***
SPECIAL ROUTE ran on directory: /home/mchiama6/spiketrum
SPECIAL ROUTE ran on machine: allman (Linux 3.10.0-1160.76.1.el7.x86_64 Xeon 2.93Ghz)

Begin option processing ...
srouteConnectPowerBump set to false
routeSelectNet set to "VSS"
routeSpecial set to true
srouteBlockPin set to "useLef"
srouteBottomLayerLimit set to 1
srouteBottomTargetLayerLimit set to 1
srouteConnectConverterPin set to false
srouteCrossoverViaBottomLayer set to 1
srouteCrossoverViaTopLayer set to 5
srouteFloatingStripeTarget set to "blockring padring ring stripe ringpin blockpin foll owpin"
srouteFollowCorePinEnd set to 3
srouteJogControl set to "preferWithChanges differentLayer"
srouteNoViaOnWireShape set to "padring ring stripe blockring blockpin coverpin blockwi re corewire followpin iowire"
sroutePadPinAllPorts set to true
sroutePreserveExistingRoutes set to true
srouteRoutePowerBarPortOnBothDir set to true
srouteStopBlockPin set to "nearestTarget"
srouteTopLayerLimit set to 5
srouteTopTargetLayerLimit set to 5
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 3999.00 megs.

Reading DB technology information...
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
Read in 11 layers, 5 routing layers, 1 overlap layer
Read in 570 macros, 83 used
Read in 277 components
81 core components: 81 unplaced, 0 placed, 0 fixed
196 pad components: 0 unplaced, 0 placed, 196 fixed
Read in 182 physical pins
182 physical pins: 0 unplaced, 0 placed, 182 fixed
Read in 182 nets
Read in 2 special nets, 2 routed
Read in 263 terminals
1 net selected.

Begin power routing ...
**WARN: (IMPSR-1254): Unable to connect the specified objects, since block pins of t he VSS net were not found in the design. Check netlist or change the parameter value t o include block pins in the design.
**WARN: (IMPSR-1256): Unable to find any CORE class pad pin of the VSS net due to un availability of the pin or check netlist in the routing area or layer. Change routing area or layer to include the expected pin or check netlist. Alternatively, change port class in the technology file.
Type 'man IMPSR-1256' for more detail.
Cannot find any AREAIO class pad pin of net VSS. Check net list, or change port class in the technology file, or change option to include pin in given range.
CPU time for VSS FollowPin 0 seconds
Number of IO ports routed: 0
Number of Block ports routed: 0
Number of Stripe ports routed: 0
Number of Core ports routed: 0
Number of Pad ports routed: 0
Number of Power Bump ports routed: 0
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 4001.00 megs.

Begin updating DB with routing results ...
Updating DB with 182 io pins ...
Updating DB with 0 via definition ...
sroute created 0 wire.
ViaGen created 0 via, deleted 0 via to avoid violation.

I'm not sure where to start from, the netlist is generated using Genus from a VHDL RTL code. In my RTL design, I have VDD and VSS inout pins. 

Thanks for you help. 

Anas

The WARN: (IMPSR-1256) tells you that sRoute does not see a pad pin that should be connected to the VSS net. So you have to check if your VSS PADS have their pins in the selected routing range, and if they are logically connected to the VSS net, by running globalNetConnect for example.

Hi Dimo, 

Thanks for your reply! 

I tried running the following commands only: 

setMultiCpuUsage -localCpu max

set module chip

set_global _enable_mmmc_by_default_flow $CTE::mmmc_default
suppressMessage ENCEXT-2799

getDrawView
loadWorkspace -name Physical

set ::TimeLib::tsgMarkCellLatchConstructFlag 1
set _timing_save_restore_compression_mode hybrid
set degHonorSignalNetNDR 1
set defHierChar /
set delaycal_input_transition_delay 0.1ps
set distributed_client_message_echo 1
set distributed_mmmc_disable_reports_auto_redirection 0
set fpIsMaxIoHeight 5
set gpsPrivate::dpgNewAddBufsDBUpdate 1
set gpsPrivate::lsgEnableNewDbApilnRestruct 1

## change the folowing file
set init_io_file padframe.io

## change the folowing file
set init_lef_file {/eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tcb018gbwp7t_270a/lef/tcb018gbwp7t_5lm.lef /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tpd018bcdnv5_160a/mt/5lm/lef/tpd018bcdnv5_5lm.lef}

## change the folowing file
set init_mmmc_file viewDefinition_chip.tcl

set init_oa_search_lib {}

## change the folowing file
set init_verilog chip_m.v

set latch_time_borrow_mode max_borrow
set 1sg0CPGainMult 1.390000
set pegDefaultResScaleFactor 1.900000
set pegDetailResScaleFactor 1.990000
set report_inactive_arcs_format {from to when arc_type sense reason}
set timing_library_float_precision_tol 0.900010
set timing_library_load_pin_cap_indices {}
set timing_library_write_library_to_directory {}
set tso_post_client_restore_command {update_timing ; write_eco_opt_db ;}

setDesignMode -process 180

set init_gnd_net {VSS}
set init_pwr_net {VDD}
init_design
globalNetConnect VDD -type pgpin -pin VDD -all
globalNetConnect VSS -type pgpin -pin VSS -all

The tool shows no errors when applying (globalNetConnect VSS -type pgpin -pin VSS -all), but it shows the following error when applying (globalNetConnect VDD -type pgpin -pin VDD -all):

**ERROR: (IMPDB-1216):  The global net 'VDD' specified in the global net connection(GNC) rule doesn't exist in the design.

Both signals are left unconnected after routing finishes. I don't understand why it doesn't recognize the VDD siganl. Power signals are defined in the RTL code as inout std_logic_vector(7 downto 0), do I have to reference individual bits somehow? 

Many thanks

Anas

Also, all cells show a metal_short DRC error for the VDD signal. This is another issue (may not be related to this post), but clearly, there is a problem with the VDD signal that is fundamental to going forward with the layout. 

I have verified the power pads for the cells in the .lef file, and it is actually called "VDD". I don't understand where the short is coming from. 

Kind regards,

Anas

Please check your log file for warnings/errors during init_design. There is something off with your PG nets and global connections. You cannot proceed with the flow until this is fixed.
I think you already discussed this issue in another thread. 

Also I find this uncanonical "Power signals are defined in the RTL code as inout std_logic_vector(7 downto 0)". Do you need explicit PG pins, and if you do you best use regular ports with dedicated names.

Hi Dimo, Thanks for your help. 

What is the ideal way to define the PG pins for your design? Of course, the IC needs multiple of power and ground pins, how should I be connecting PG nets in my design to the outside world? 

Many thanks ^_^

Anas

When I run the following:

set init_pwr_net {VDD}

set init_gnd_net {VSS}

init_design

# Connect Global VSS

globalNetConnect VSS -type tielo -pin VSS -all -verbose

globalNetConnect VSS -type pgpin -pin VSS -all -verbose

# Connect Global VDD

globalNetConnect VDD -type tiehi -pin VDD -all -verbose

globalNetConnect VDD -type pgpin -pin VDD -all -verbose

The tool shows no problems for VSS, and reports “new gnd-pin connection was made to global net 'VSS’ ”. However, after running the commands for VDD, this error message is reported:

*ERROR: (IMPDB-1216):  The global net 'VDD' specified in the global net connection(GNC) rule doesn't exist in the design.

This is strange as I can find the signal in Route -> Special Route -> Nets, and stripes across the VDD ring are actually made.

What could cause the tool not to recognise the VDD signal in the design? 

I just managed to solve the problem by deleting the VDD and VSS ports from the RTL design.

Thanks for the help!

Anas