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Proper Timing Analysis using Innovus (and Genus)

Anas2023a95

Dear all, 

I need some guidance on how to perform a proper timing analysis in Innovus to ensure all paths meet the performance requirements. 

First, in my Innovus scripts, I feed the design (.v file) and the constraints (.sdc file) which both are generated from Genus. I also use the .lib files of the STD cells to create an MMMC file and read it before initiating the design.

Then I run the following commands to perform timing analysis at different stages of the flow:

set_ccopt_property target_max_trans 0.294
set_ccopt_property target_skew 1

setCTSMode -engine ccopt


create_ccopt_clock_tree -name clk -source clk
ccopt_design

## report clock trees and skew groups
report_ccopt_clock_trees -file reports/$module/clock_trees.rpt
report_ccopt_skew_groups -file reports/$module/skew_groups.rpt


## report timing after CTS
report_timing -unconstrained -delay_limit 1 > reports/$module/timing_report_postCCopt.prt

However, when I check the Hold time (for example), the tool show (N/A) next to the timing value. I'm assuming that there is something wrong I'm doing.

Also, I'm not sure how to tell the tool that the 'clk' signal is a clock - not a normal input. How should I be defining the clock signal? Is it only through the .sdc file as it is currently done? Once I define the clock properly, will the tool automatically insert clock repeaters (or clock splitters) to meet timing requirements and prevent issues like clock skewing? 

Many thanks

Anas

-----------------------------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------------------------

The MMMC file: 


set lib /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcb018gbwp7t_270a

create_library_set -name fast\
-timing\
[list $lib/tcb018gbwp7tbc.lib]


create_library_set -name slow\
-timing\
[list $lib/tcb018gbwp7twc.lib]

create_constraint_mode -name my_constraint_mode\
-sdc_files /home/mchiama6/spiketrum/chip_m.sdc

create_rc_corner -name my_rc_corner\
-preRoute_res 1\
-postRoute_res 1\
-preRoute_cap 1\
-postRoute_cap 1\
-postRoute_xcap 1\
-preRoute_clkres 0\
-preRoute_clkcap 0\
-T 25\
-cap_table /eda/design_kits/180n_FORTE_v3/PDK_v02_1.6b_2021/tsmc_libraries/TSMCHOME/digital/Back_End/lef/tcb018gbwp7t_270a/techfiles/captable/t018lo_1p5m_typical.captable\
-qx_tech_file /home/chip/qrcTechFile


create_delay_corner -name my_delay_corner_slow \
-library_set {slow} \
-rc_corner my_rc_corner

create_delay_corner -name my_delay_corner_fast \
-library_set {fast} \
-rc_corner my_rc_corner

create_analysis_view -name my_analysis_view_setup \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_fast

create_analysis_view -name my_analysis_view_hold \
-constraint_mode my_constraint_mode \
-delay_corner my_delay_corner_slow

set_analysis_view \
-setup {my_analysis_view_setup} \
-hold {my_analysis_view_hold}

-----------------------------------------------------------------------------------------------------------------------------

The .sdc file (Main commands):

# ####################################################################

# Created by Genus(TM) Synthesis Solution 21.10-p002_1 on Sat Mar 25 17:42:40 GMT 2023

# ####################################################################

set sdc_version 2.0

set_units -capacitance 1000fF
set_units -time 1000ps

current_design chip

create_clock -name "clk" -period 0.005 -waveform {0.0 0.0025}
group_path -weight 1.000000 -name C2C -from [list \
[get_cells {Subtractor/sig3_reg[5]}]


group_path -weight 1.000000 -name C2O -from [list \
[get_cells {Subtractor/sig3_reg[5]}] \
[get_cells {spike_generator_temp3_reg[2]}] ] -to [list \
[get_ports Con_Valid] \
[get_ports {Con_out[12]}] \
[get_ports {Con_out[11]}] \


group_path -weight 1.000000 -name I2C -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_cells RC_CG_DECLONE_HIER_INST/RC_CGIC_INST] ]


group_path -weight 1.000000 -name I2O -from [list \
[get_ports clk] \
[get_ports reset] \
[get_ports IN_Valid] \
[get_pins RC_CG_DECLONE_HIER_INST/enable] \
[get_pins RC_CG_DECLONE_HIER_INST/RC_CGIC_INST/E] ]
set_clock_gating_check -setup 0.0
set_clock_latency -max 0.005 [get_ports clk]
set_clock_latency -source -max 0.001 [get_ports clk]

-----------------------------------------------------------------------------------------------------------------------------

Parents
  • Anas2023a95 said:
    Also, I'm not sure how to tell the tool that the 'clk' signal is a clock - not a normal input. How should I be defining the clock signal? Is it only through the .sdc file as it is currently done?

    Yes, this is correct, Innovus will create its default clock tree specification based on the clocks defined in the SDC file. The clock tree specification is what is used during CTS as a cookbook. Btw you do not need to do this "create_ccopt_clock_tree -name clk -source clk", clock trees are automatically defined for each sdc clock.
    I suggest you to read the Chapter Clock Tree Synthesis from the Innovus UG for better understanding of how CTS is working.


    When you want to report hold timing, you need to do "report_timing -check_type hold".

    A side note: If I read your SDC constraints correctly, you are creating a clock with 5ps period. This is a bit ... ambitious.

    - Dimo

  • in reply to DimoM

    Hi Dimo, 

    Thank you very much for your great help during the past couple of days! 

    I have updated my SDC file as the following for a 5-ns-period clock - thanks for pointing out the ps-clock issue Sweat smile:

    create_clock -name "clk" -period 5 -waveform {0.0 2.5} [get_ports {clk}]
    set_clock_uncertainty 0.2 [get_ports {clk}]
    set_clock_latency -source 2 [get_ports {clk}]
    set_clock_latency 1.5 [get_ports {clk}]
    set_clock_transition 0.3 [get_clocks {clk}]

    set_input_delay 1.0 [get_clocks {*}]
    set_output_delay 2.0 [get_clocks {*}]

    I have also created a ctstch file, as the following:

    ClkGrp
    +clk

    RouteTypeName CLK_ROUTE
    TopPreferredLayer 5
    BottomPreferredLayer 3
    NonDefaultRule WideWire
    PreferredExtraSpace 0
    End

    #------------------------------------------------------------
    # Clock Root : clk
    # Clock Name : clk
    # Clock Period : 5ns
    #------------------------------------------------------------
    AutoCTSRootPin clk
    Period 5ns
    MaxDelay 5ns
    MinDelay 0ns
    MaxSkew 150ps
    SinkMaxTran 200ps
    BufMaxTran 200ps
    AddDriverCell CLKBUFX16
    Buffer INVD3BWP7T INVD4BWP7T INVD5BWP7T INVD6BWP7T INVD7BWP7T INVD8BWP7T
    NoGating NO
    DetailReport YES
    SetDPinAsSync YES
    SetIoPinAsSync YES
    RouteClkNet YES
    RouteType CLK_ROUTE
    END

    In my script, I run the CTS and the optimization process as the following:

    placeDesign

    placeDesign -incremental

    optDesign -preCTS -incr

    clockDesign -specFile Clock.ctstch -outDir clock_report -fixedInstBeforeCTS

    setCTSMode -engine ccopt

    ccopt_design

    setOptMode -fixCap true -fixTran true -fixFanoutLoad false
    optDesign -preCTS
    optDesign -postCTS

    routeDesign -globalDetail

    The results I have are: 

    1) 

    I'm assuming this means that there are no violation paths in the design and it should be able to run at 200 MHz, right?

    2) 

    This is the synthesised clock tree, do the green circles indicate the added splitters and the green triangles indicate the added buffers? 

    Can I assume now that the design passes the timing requirements? 

    Thank you very much! 

    Anas 

  • in reply to Anas2023a95

    Hi Anas,

    which tool version you are using ? The clockDesign command and using ctstch has been deprecated for quite some time now.

    This video demonstrates how to use the clock tree debugger : How to use the Clock Tree Debugger in the Innovus Software (Video)
    If you expand the Key (the button on the upper left) you will see a description of every object used in the clock tree visualization.

    The structure of the clock tree is puzzling, having this horizontal line on the top means that there is no delay; the vertical axis represents time.
    You might have some ideal nets left in the design after CTS for some reason.

    Also you have to time/optimize your design after routing to account for the effects of the detailed routes.

    - Dimo

  • in reply to DimoM

    Hi Dimo, 

    Thank you for your reply! 

    I'm using version 21.11. 

    I have replaced the use of ctstch by the following code (including PnR scripts):

    ### Placement of Standard Cells.....without any optimization......
    setPlaceMode -fp false
    placeDesign -noPrePlaceOpt

    ### Setting for preCTS......
    setDelayCalMode -siAware false
    timeDesign -preCTS
    report_timing
    optDesign -preCTS

    ### Clock Tree Synthesis.........
    create_ccopt_clock_tree_spec
    ccopt_design

    ### Post CTS Optimization.....
    timeDesign -postCTS
    optDesign -postCTS
    timeDesign -postCTS

    #####nanoroute...........turnoff Fix antenna
    setNanoRouteMode -quiet -timingEngine {}
    setNanoRouteMode -quiet -routeWithTimingDriven 1
    setNanoRouteMode -quiet -routeWithSiDriven 1
    setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
    setNanoRouteMode -quiet -drouteStartIteration default
    setNanoRouteMode -quiet -routeTopRoutingLayer default
    setNanoRouteMode -quiet -routeBottomRoutingLayer default
    setNanoRouteMode -quiet -drouteEndIteration default
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithSiDriven true
    routeDesign -globalDetail

    setEndCapMode -reset
    setEndCapMode -boundary_tap false
    setNanoRouteMode -quiet -routeAntennaCellName {}
    setUsefulSkewMode -maxSkew false -noBoundary false -useCells {CKBD0BWP7T CKBD1BWP7T CKBD2BWP7T CKBD3BWP7T CKBD4BWP7T CKBD6BWP7T CKBD8BWP7T CKBD10BWP7T CKBD12BWP7T} -maxAllowedDelay 1
    setNanoRouteMode -quiet -routeAntennaCellName adiode
    setNanoRouteMode -quiet -routeTdrEffort 5
    setNanoRouteMode -quiet -routeTopRoutingLayer default
    setNanoRouteMode -quiet -routeBottomRoutingLayer default
    setNanoRouteMode -quiet -drouteEndIteration default
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithSiDriven true
    routeDesign -globalDetail -viaOpt -wireOpt

    ### Post Route Anlysis.......0.0
    setAnalysisMode -analysisType onChipVariation
    timeDesign -postRoute
    optDesign -postRoute -hold

    timeDesign -postRoute
    report_timing
    setAnalysisMode -checkType hold
    report_timing
    report_power
    report_constraint -all_violators
    report_ccopt_skew_groups

    I have some violating paths now, so I'm assuming the effort level is now less? 

    Yeah, the horizontal line (which is "clk" net) in the clock tree doesn't look right. Also, shouldn't the vertical axis of the clock tree start from 0s? It is starting at 2, any idea why? I used this command to find the ideal nets in the design and I can only see false what is reported:

    get_property [get_nets] is_ideal

    How would the clock have been defined as ideal? I'm only defining the clock now in the SDC file.

    Any thoughts on what has possibly gone wrong?

    Thank you!

    Anas

Reply
  • in reply to DimoM

    Hi Dimo, 

    Thank you for your reply! 

    I'm using version 21.11. 

    I have replaced the use of ctstch by the following code (including PnR scripts):

    ### Placement of Standard Cells.....without any optimization......
    setPlaceMode -fp false
    placeDesign -noPrePlaceOpt

    ### Setting for preCTS......
    setDelayCalMode -siAware false
    timeDesign -preCTS
    report_timing
    optDesign -preCTS

    ### Clock Tree Synthesis.........
    create_ccopt_clock_tree_spec
    ccopt_design

    ### Post CTS Optimization.....
    timeDesign -postCTS
    optDesign -postCTS
    timeDesign -postCTS

    #####nanoroute...........turnoff Fix antenna
    setNanoRouteMode -quiet -timingEngine {}
    setNanoRouteMode -quiet -routeWithTimingDriven 1
    setNanoRouteMode -quiet -routeWithSiDriven 1
    setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
    setNanoRouteMode -quiet -drouteStartIteration default
    setNanoRouteMode -quiet -routeTopRoutingLayer default
    setNanoRouteMode -quiet -routeBottomRoutingLayer default
    setNanoRouteMode -quiet -drouteEndIteration default
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithSiDriven true
    routeDesign -globalDetail

    setEndCapMode -reset
    setEndCapMode -boundary_tap false
    setNanoRouteMode -quiet -routeAntennaCellName {}
    setUsefulSkewMode -maxSkew false -noBoundary false -useCells {CKBD0BWP7T CKBD1BWP7T CKBD2BWP7T CKBD3BWP7T CKBD4BWP7T CKBD6BWP7T CKBD8BWP7T CKBD10BWP7T CKBD12BWP7T} -maxAllowedDelay 1
    setNanoRouteMode -quiet -routeAntennaCellName adiode
    setNanoRouteMode -quiet -routeTdrEffort 5
    setNanoRouteMode -quiet -routeTopRoutingLayer default
    setNanoRouteMode -quiet -routeBottomRoutingLayer default
    setNanoRouteMode -quiet -drouteEndIteration default
    setNanoRouteMode -quiet -routeWithTimingDriven true
    setNanoRouteMode -quiet -routeWithSiDriven true
    routeDesign -globalDetail -viaOpt -wireOpt

    ### Post Route Anlysis.......0.0
    setAnalysisMode -analysisType onChipVariation
    timeDesign -postRoute
    optDesign -postRoute -hold

    timeDesign -postRoute
    report_timing
    setAnalysisMode -checkType hold
    report_timing
    report_power
    report_constraint -all_violators
    report_ccopt_skew_groups

    I have some violating paths now, so I'm assuming the effort level is now less? 

    Yeah, the horizontal line (which is "clk" net) in the clock tree doesn't look right. Also, shouldn't the vertical axis of the clock tree start from 0s? It is starting at 2, any idea why? I used this command to find the ideal nets in the design and I can only see false what is reported:

    get_property [get_nets] is_ideal

    How would the clock have been defined as ideal? I'm only defining the clock now in the SDC file.

    Any thoughts on what has possibly gone wrong?

    Thank you!

    Anas

Children
  • in reply to Anas2023a95

    Hi,

    seems like post-route you are running only hold optimization. Instead, try running optDesign -postRoute -setup -hold  instead, maybe will help cleaning up some violations. But I would not be bothered too much to close the timing when there is something off with the general setup.

    Try to understand what is happening with CTS and why the clock tree looks like that. A few things you can do >
    Read the log file, when ccopt is running. It is informative, you can see what it is doing at each step, what targets it is using, and it does some intermediate reporting.  In the same time look for any warnings that might hint to the problem.

    Also report some paths with  "report_timing -path_type full_clock -net". This way you can look at the clock nets and see if they have real delays that make sense. 
    You can se the timing format to see fanout, load and slews with a command like this one :
    set report_timing_format {timing_point cell arc fanout load slew delay incr_delay arrival pin_location }

    Another thing you can do is try to propagate the clocks explicitly after CTS, with set_propagated_clock [all_clocks].

    - Dimo

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