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Convergence issue while simulating CNTFET adder

Aalelai

Sir,

I'm working on CNTFET-based arithmetic circuits. Initially, I developed all the basic ternary logic gates using 45nm CNTFET and they were working correctly. But when I tried to simulate a half-adder, using the same, it threw an error. The total transient analysis time was 10 us, but the simulation ran only up to 2 us. Kindly help me in rectifying the same. FYI, CNTFET was a VerilogA model and it was imported into Virtuoso. 

 Error:

Error found by spectre at time = 2.017 us during transient analysis `tran'.

    ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. 

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