Stats

  • Locked Locked
  • Replies 1
  • Subscribers 94
  • Views 6063
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

2D registers

gpeyton

Hi,

I have a 2D register. Before synthesis it looks like this

module SPI
(
...
output logic [7:0] REG_DATA [7:0]
);

After synthesis it gets flattened like this:

module SPI(... REG_DATA);
...
output [63:0] REG_DATA;
I need to keep track of each 2D register name to make routing easier later, so how would I change this to synthesize into something more usable like the following?
output [7:0] REG_DATA0;
...
output [7:0] REG_DATA7;

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.