I have an RTL design synthesized by Genus, and placed and routed by Innovus.
In the process of verifying the design, I was thinking of running Corner Analysis. I have done such analysis before using Virtuoso for a schematic view design. So, I started thinking about how I could convert the netlist generated by Genus to a schematic that I could open in Virtuoso and run the different simulations. I tried using the Verilog In tool in Virtuoso (File -> Import -> Verilog) but that didn't quite work.
@(#)$CDS: ihdl version 6.1.8-64b 10/05/2021 19:14 (cpgsrv11) $ Wed Aug 30 15:49:50 2023
INFO (VERILOGIN-589): Using xmvlog binary for compilation.ERROR (VERILOGIN-540): visadev load failedINFO (VERILOGIN-206): End of Logfile.
Any suggestions? Many thanks.
Consider exploring options for netlist conversion or simulation tool compatibility. You might find success with tools like Cadence's NC-Sim or Synopsys' VCS, which are better suited for RTL simulation and analysis, allowing for a smoother transition from Genus to Virtuoso. Also, check out AC Football Cases