Stats

  • Locked Locked
  • Replies 1
  • Subscribers 92
  • Views 8149
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog netlist to Schematics

Anas2023a95

Dear all, 

I have an RTL design synthesized by Genus, and placed and routed by Innovus.

In the process of verifying the design, I was thinking of running Corner Analysis. I have done such analysis before using Virtuoso for a schematic view design. 
So, I started thinking about how I could convert the netlist generated by Genus to a schematic that I could open in Virtuoso and run the different simulations. 
I tried using the Verilog In tool in Virtuoso (File -> Import -> Verilog) but that didn't quite work.

Log output: 

@(#)$CDS: ihdl version 6.1.8-64b 10/05/2021 19:14 (cpgsrv11) $ Wed Aug 30 15:49:50 2023

INFO (VERILOGIN-589): Using xmvlog binary for compilation.
ERROR (VERILOGIN-540): visadev load failed
INFO (VERILOGIN-206): End of Logfile.

Any suggestions? Many thanks.

Kind regards,

Anas

  • Consider exploring options for netlist conversion or simulation tool compatibility. You might find success with tools like Cadence's NC-Sim or Synopsys' VCS, which are better suited for RTL simulation and analysis, allowing for a smoother transition from Genus to Virtuoso. Also, check out AC Football Cases

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.