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How to make sure Genus does not insert buffers with on/off VDD in a signal's network?

2tojohny

Hi,

I have 2 power domains: AON and OOD, where AON is always-on VDD and OOD is VDD that can be turned on and off.  A signal "ret1n" is generated by logic in the AON domain (VDD is always on).  "ret1n" travels to other modules in the design.  Some of these modules are in the OOD power domain.  How to constrain Genus from placing buffers using the OOD VDD on "ret1n" when it has to connect to cells in the OOD domain?  In other words, how to make sure synthesis only connects timing optimization or power optimization changes using AON VDD in all parts of the "ret1n" signal distribution network?

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