Failed to synthesis RISCY core on genus legacy.

Hi, after trying to synthesis the RISCY core in genus legacy tool, I'm getting the following error. It says the 'cv32e40p_apu_core_pkg' is missing. But I already included it along with the RTL. Also all the files are in system verilog. 

Can anyone help me with this. We are trying to benchmark RISCY core by obtaining power, area and time etc.

Error : Reference to non-existent package. [VLOGPT-28] [read_hdl]
: Reference to non-existent package 'cv32e40p_apu_core_pkg' in file '/home/user1/amal/risc_Y/src/cv32e40p_core.sv' on line 31, column 49.
: The referenced package does not exist.
output logic [APU_NARGS_CPU-1:0][31:0] apu_operands_o,

This is the TCL script i used.

set DESIGN cv32e40p_core
set_attribute information_level 7

set_attribute init_lib_search_path {/home/install/FOUNDRY/digital/45nm/dig/lib/slow.lib}
set_attribute init_hdl_search_path {/home/user1/amal/risc_Y/src}
#read_libs

#set_attribute library $lib

set a {\
cv32e40p_core.sv \
cv32e40p_apu_core_pkg.sv \
cv32e40p_fpu_pkg.sv \
cv32e40p_pkg.sv \
cv32e40p_sleep_unit.sv \
cv32e40p_if_stage.sv \
cv32e40p_prefetch_buffer_i.sv \
cv32e40p_prefetch_controller.sv \
cv32e40p_fifo.sv \
cv32840p_obi_interface.sv \
cv32e40p_aligner.sv \
cv32e40p_compressed_decoder.sv \
cv32e40p_id_stage.sv \
cv32e40p_register_file_latch.sv \
cv32e40p_decoder.sv \
cv32e40p_controller.sv \
cv32840p_int_controller.sv \
cv32e40p_hwloop_regs.sv \
cv32e40p_ex_stage.sv \
cv32e40p_alu.sv \
cv32e40p_ff_one.sv \
cv32e40p_alu_div.sv \
cv32e40p_mult.sv \
cv32e40p_apu_disp.sv \
cv32e40p_load_store_unit.sv \
cv32e40p_obi_interface.sv \
cv32e40p_cs_registers.sv \
cv32e40p_pmp.sv \
cv32e40p_popcnt.sv \
cv32e40p_sim_clock_gate.sv
}

read_hdl -sv $a
elaborate $DESIGN
current_design cv32e40p_core

create_clock -period 5 -name CLK [get_ports {clk_i}]
set_input_delay -max 1.67 ["all_inputs"] -clock CLK
set_output_delay -max 1.67 ["all_outputs"] -clock CLK
set_clock_uncertainty 0.25 [get_clock CLK]
set_max_transition 0.25
set_max_capacitance 0.4 ["all_outputs"]
set_max_fanout 32 ["all_inputs"]

check_design
set_attribute syn_generic_effort medium
syn_generic
report summary

set_attribute syn_map_effort medium
syn_map
report summary

set_attribute syn_opt_effort medium
syn_opt
report summary

report_timing > /home/user1/amal/risc_Y/reports/timingcore.rpt
report_power > /home/user1/amal/risc_Y/reports/powercore.rpt
report_area > /home/user1/amal/risc_Y/reports/areacore.rpt
report_qor > /home/user1/amal/risc_Y/reports/qorcore.rpt
report_timing -num_paths 200000 > /home/user1/amal/risc_Y/reports/timing_num_pathccore.rpt
report_timing -from [all_inputs] -to [all_registers] > /home/user1/amal/risc_Y/reports/report_input2reg.txt
report_timing -from [all_registers] -to [all_registers] > /home/user1/amal/risc_Y/reports/report_reg2reg.txt
report_timing -from [all_registers] -to [all_outputs] > /home/user1/amal/risc_Y/reports/report_reg2output.txt
report_timing -from [all inputs] -to [all_outputs] > /home/user1/amal/risc_Y/reports/report_input2output.txt

write_hdl > /home/user1/amal/risc_Y/outputs/netlistcore.v
write_sdc > /home/user1/amal/risc_Y/outputs/sdccore.sdc
#write_db > /home/soorajm/Documents/genus/Outputs/sdcmkccore12nm.db