Stats

  • Locked Locked
  • Replies 0
  • Subscribers 91
  • Views 4246
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Genus netlist generation (write_hdl) takes very long time

ACMTUG

Hi,

I am trying to synthesize a relatively large design (consuming ~56mm^2) using Cadence genus211_21.15. 

Design involves many gate-level operations and I'm using already generated netlists as submodules (by reading them using "read_netlist") to speedup the synthesis runtime.

I also use "preserve" and "ungroup" to further improve synthesis time. This indeed improves the synthesis time significantly.

However, netlist generation (write_hdl) takes very very long time. 

For a smaller design, the same approaches finished the synthesis in ~30 minutes; however, netlist generation took 3 days! (The size of final netlist verilog file is only 600KB).

Did anyone face similar issue? I'll appreciate any suggestion to solve this issue.

Thanks.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.