Synthesis Issue: Large Netlist Size Due to Missing Memory Libraries

Hi,
I am currently designing a block where I capture 1024 samples, each sample being 64 bits wide, and store them into a FIFO structure backed by SRAM.
During synthesis, I am observing that the resulting netlist has an unexpectedly large number of cells (~800K–900K cells).

I suspect the problem is due to the absence of memory compiler libraries (SRAM macros), so the synthesis tool is building large memories out of flip-flops instead of mapping to real SRAM instances.

I would like to know:

• How should I properly set up and link memory libraries (.lib, .lef, .v) in Cadence Genus?

• Are there specific compile options to ensure memories are inferred or instantiated properly?

• Where can I find or access the RAM or other macro libraries needed for synthesis (especially as someone new to Cadence)?

• Is the issue I have described here actually the root cause, or is there something else I should be aware of that could be causing the problem?

I am fairly new to Cadence tools and still learning, so any guidance on the correct flow or documentation references would be really helpful!

Thanks in advance!