Glitch in Synthesized Netlist Simulation of SR Latch — Occurs Only in One Instance

Hi all,

I’m facing an unexpected glitch during post-synthesis netlist simulation of a design that includes multiple instances of an SR latch. I’ve attached both the netlist snapshot and the SimVision waveform for reference.

Originally, the latch was modelled at the gate level using NOR-based feedback:

The post layout netlist looks as follows

module SR_Latch_8 (

Q,

RESET,

SET);

output Q;

input RESET;

input SET;

// Internal wires

wire QBAR;

wire n_2;

BUFM2R cdn_unmapped_dis_arc_buf (.A(Q),

.Z(n_2));

NR2M12RA g22__7098 (.A(RESET),

.B(QBAR),

.Z(Q));

NR2M6R g23__6131 (.A(n_2),

.B(SET),

.Z(QBAR));

endmodule

   The glitch happens during synthesized netlist simulation, not in RTL simulation. It appears at a specific time where SET=0 and RESET=0, i.e., the latch should hold its previous value. The output (Q) transitions momentarily when it shouldn't, possibly violating the hold condition. Timing reports do not indicate setup/hold violations. Zero-delay simulation is being used, but even with gate delays inserted, the behavior remains. Initial values are correctly applied and testbench sequences are consistent. I suspect this might be related to the feedback handling or synthesis optimization — but I’m not sure why only one instance would misbehave.

To simplify and improve simulation behavior, I rewrote the latch in a behavioral style, avoiding explicit feedback and modeling expected functional output. However, the glitch still persists in the same instance, and only that one — all other identical SR latch instances simulate as expected with the same testbench.

Has anyone seen this type of issue before or can help pinpoint what's going wrong here?

 Any help or suggestions would be greatly appreciated!

Thanks
Saranya