Tracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus

Hi Cadence Community,

I'm using Genus 21 to synthesize a design and need help with two goals:

1. Tracing gates to RTL lines: I've set set_attribute hdl_track_filename_row_col true, which enables RTL source tracking in report_gate -source. This attribute set works, but I want get the information about each gate that they came from which line of my RTL code.
   
   
2. Preserving module info in gate names: After flattening with ungroup -flatten -all, I want gate names to reflect their originating modules. I tried set_attribute hdl_flatten_naming_style module_path, but got an error: "Invalid attribute name [TUI-40]". Is this attribute unsupported in my version, or is there an alternative to embed module names in a flattened netlist?

My script includes write_hdl -source > ${design}_RTL_track/netlist_final/${design}_syn.v  for writing netlist. Thanks!