How to manage block-level and top-level SDC constraints?

I am currently facing some issues trying perform a hierarchical implementation of a chip with Cadence tools, particularly on how to manage timing constraints.
The chip includes a few digital blocks which are independently synthesized with block-level constraints (with multiple modes defined), while their size and position in the chip is defined by the top-level partitioning, which also pushes down top-level constraints. 

Let me detail the steps I follow in my flow.

Block synthesis script (for the synthesis of each digital block) in Genus:
1. Synthesize the block design with block-level constraints (having multiple modes defined)
2. Output the netlist, and the updated constraints with write_mmmc command

Top level script (for partitioning) in Innovus:
1. Import digital block netlists from previous Genus script.
2. Create the top level floorplan, place the macros and define the digital partition area, run power routing (rings and stripes)
3. Push down top level constraints to the digital partitions with deriveTimingBudget and saveTimingBudget commands. Then, commit the partitions.
4. Route the partition signals to each others and to the macros, then save the design.

After this, I would like to implement (PnR) the block in Innovus by loading the generated partition, the pushed-down constraints and the block-level constraints. However, I don't understand how should I merge the top-level constraints (generated by saveTimingBudget) with the block-level constraints (generated by genus starting from my original hand-written sdc). In particular, at this step, I find myself with:
- top-level constraints which are automatically loaded when I load the partition in Innovus, defining two modes: one for setup and one for hold (despite the fact that I defined only one in my top-chip level script for both setup and hold!)
- block-level constraints generated by genus, which are associated with different modes

Is this flow the correct one for hierarchical implementation? The Innovus User Guide is not very clear about how to perform synthesis and how to manage the constraints.

For managing the constraints, should I promote them to top-chip level and run an Innovus partitioning again or should I instead merge the block-level ones in the Innovus partition during PnR?

I patiently wait for help. Thank you