Residual power in whole design vs summed gate groups in Joules, even with full instance coverage

Hi everyone,

I'm running power analysis in Joules (Version v21.19) using simulation-based activity from a VCD file for a purely combinational design (ISCAS-85 c432). To understand the power contribution of different parts of the circuit, I split the gate-level netlist into two groups: odd and even gates, Based on their gate IDs (i.e., simply splitting them). Every single cell instance in the netlist is assigned to exactly one of these two groups; there is no gate left unaccounted for.

I then use Joules to compute:

• Power of the entire design
• Power of just the odd gate group
• Power of just the even gate group

At key simulation times (e.g., 21 ns, when input vectors change), I observe a significant difference between:

Total power reported by Joules vs. Sum of power of `odd` and `even` gate groups

For example, at 21 ns:

• Whole design power = 0.000438382069755 W

• Odd group power = 0.000196574924795 W

• Even group power = 0.000208780383976 W

• Residual = ~33 µW

Despite confirming that:

• All cell instances in the design are included across both groups

• There are no flops, clock trees, or unlisted primitives

• The switching activity is fully captured from gate-level simulation

• There is no sequential logic or memory macro in this design

I still observe this non-zero residual power.

My questions:
1) Where is the extra power coming from in the "whole" design that is not reflected in the sum of gate groups?
2) Is Joules attributing interconnect (net-level) switching power or glitching activity separately from gate instance power?

I also observed these results even in other designs.

I appreciate your help in advance.

Best regards,
Saeid

You can find the commands that I am calculating the power: