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Is there a way to disable specific timing checks

MaurizioCDN

Hi,

we are doing a gate-level simulation with back-annotated SDF file. We have some timing violations on resynchronization FF.s between 2 different clock domains. Violations causes X to propagate all ovewr the circuit causing simulation to fail. In reality X will not propagate since double-synchronization ensure that possible meta-stability will resolve.

Is it possible to instruct simulation tool to disable notifier/timing checks for a specific instance ( w/o haciking SDF file)?

Thanks
Maurizio Spadari

 

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