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How to mirror VHDL signal in verilog Top Test bench

Hi I am writing a test bench to test VHDL design For which I need to access few signals in the design hierarchy How to mirror them, I used nc_mirror, but got errors. Help me Thanking Venkat Reddy Uppala

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tpylant over 17 years ago

What kind of problem are you having? There is pretty good documentation on nc_mirror in the NC-Verilog and NC-VHDL manuals if you just need some examples.

Tim
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tpylant over 17 years ago

What kind of problem are you having? There is pretty good documentation on nc_mirror in the NC-Verilog and NC-VHDL manuals if you just need some examples.

Tim
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