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How to mirror VHDL signal in verilog Top Test bench

Sowmya Reddy

Hi I am writing a test bench to test VHDL design For which I need to access few signals in the design hierarchy How to mirror them, I used nc_mirror, but got errors. Help me Thanking Venkat Reddy Uppala

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  • Venkat,

    The problem in your case is that the path specified in your nc_mirror is not correct. You need to get the correct path.

    The most likely cause seems to be that the vhdl top path starts with a ":" So instead of the top level entity/architecture, you replace it with ":"

    Moreover, there are a few easy ways to find out the correct path with the help of tool:

    a) Open the Simvision design browser (ncsim -gui or irun -gui) and drill down to the signal and then see its correct path from Right click menu "Describe" option. You can get the correct pathname which is printed in the console window.

    b) On the ncsim tcl prompt (ncsim -tcl or irun -tcl), confirm the path by doing "describe <objectname>" to confirm the path.

    c) Use the tcl find command to find the path name of object.

    I hope it helps.

    rgds,

    Amit.

Reply

  • Venkat,

    The problem in your case is that the path specified in your nc_mirror is not correct. You need to get the correct path.

    The most likely cause seems to be that the vhdl top path starts with a ":" So instead of the top level entity/architecture, you replace it with ":"

    Moreover, there are a few easy ways to find out the correct path with the help of tool:

    a) Open the Simvision design browser (ncsim -gui or irun -gui) and drill down to the signal and then see its correct path from Right click menu "Describe" option. You can get the correct pathname which is printed in the console window.

    b) On the ncsim tcl prompt (ncsim -tcl or irun -tcl), confirm the path by doing "describe <objectname>" to confirm the path.

    c) Use the tcl find command to find the path name of object.

    I hope it helps.

    rgds,

    Amit.

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