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long simulation time problem

eyal

hello all!

i need some advice  regarding the next scenario :

i need to verify a design that one of its task's is to scan 24k enteries memory in time interval of 1s and 10s, the design itself works at clock of 180 mhz.

the problem is that i can't simulate more than 10 ms and this itself takes about 3 hours.

i can't change the time scale of the simulation because the design is for fpga and contains the pll instansation.

i will be happy to hear from yours experience.

Eyal.

 

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  •  

    In the absence of specific details, the general performance suggestions are:

    - Look at the command line switches that can speed up the simulator. For example - -access, -linedebug switches should not be used for batch simulations.

    - Profile the simulation run (of about 10-15minutes). This can be done by simply adding "-profile" option to ncsim or irun. It generates ncprof.out and look at the areas where the actual time is being spend.

    If you can share more information about the environment (languages involved, any PLIs, RTL or gate level  etc), and the profiler output (ncprof.out), then we can help you with more performance suggestions specific to your case. Thanks.

    rgds,

    Amit.

Reply

  •  

    In the absence of specific details, the general performance suggestions are:

    - Look at the command line switches that can speed up the simulator. For example - -access, -linedebug switches should not be used for batch simulations.

    - Profile the simulation run (of about 10-15minutes). This can be done by simply adding "-profile" option to ncsim or irun. It generates ncprof.out and look at the areas where the actual time is being spend.

    If you can share more information about the environment (languages involved, any PLIs, RTL or gate level  etc), and the profiler output (ncprof.out), then we can help you with more performance suggestions specific to your case. Thanks.

    rgds,

    Amit.

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