error when passing a string to ncutils

The argument of $nc_mirror can be string or a register. Now, when it is a string, it should be the hierarchical path of the object. When it is a register then it has to be the 'actual' register. Here you are trying to pass a register whose value is expected to be treated as a string.

So, you need to either declare a string as already suggested in this thread.

 Or the other simpler way is to avoid the path_name completely. I mean, instead of first filling a path_name variable with the actual hierarchical path, pass the hierarchical path directly as string in nc_mirror argument. Please see the example below that shows this (It works with IUS6.11 version and don't need any string SV datatype).

//1.v file

Thanks everybody!

Problem solved using System Verilog and moving to IUS8.2, as tpylant suggested.


Now I have another problem when passing an string values to $nc_force during runtime. This is what I'm trying to do:

*Option 1:

reg [2:0] counter;
always @(posedge HCLK or negedge HRESETn) begin
begin
  if (!HRESETn) begin
    block_count <= 3'd5;
  end
  else
    $nc_force("path", "#block_count","verbose");
    block_count <= block_count+1;
  end
end

*Option 2:
reg [2:0] block_count;
always @(posedge HCLK or negedge HRESETn) begin
begin
  if (!HRESETn) begin
    block_count <= 3'd5;
  end
  else
    var_force= {"3'd",uitos(block_count, 10)}; 
    $nc_force("path", "#var_force","verbose");
    block_count <= block_count+1;
  end
end

function string uitos; // returns string values
begin
  input [31:0] number;
  input [31:0] base;
  string str;
...
end

ncsim reports that is forcing the 3'd5 value in both cases, but then an Internal Error occours.


Log file in both cases:

The value 3'd5 has been forced on object <path>
*** glibc detected *** ncsim: double free or corruption (!prev): 0x190e3198 ***
======= Backtrace: =========
/lib32/libc.so.6[0xf7e4c8d2]
/lib32/libc.so.6(__libc_free+0x87)[0xf7e4df67]
ncsim[0x87a9a16]
ncsim[0x87a9c21]
ncsim[0x83dd526]
[0xc0d4edc]
======= Memory map: ========
.................
fff31000-fffab000 rwxp fff31000 00:00 0                                  [stack]
.................
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 1365 NS + 16
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim   08.20-s002
  HOSTNAME: Simulator11_bcn
  OPERATING SYSTEM: Linux 2.6.19-gentoo-r5-BigSim-RAID1-lm_sensors #2 SMP Sun Apr 1 16:31:53 CEST 2007 x86_64
  MESSAGE: Unexpected signal #6, program terminated (null)
-----------------------------------------------------------------



Any idea how to do that? Or any other way to force values in verilog during runtime?