error when passing a string to ncutils

 Sorry, I would say "$nc_mirror("signal",path_name,"verbose");", without the extra character.

How about $nc_mirror("signal",{"\"",path_name,"\""},"verbose"); ?

 Shalom

Thanks for your quick reply, but still not working...

When I displayed the path_name wire, it was empty:

initial $display("signal %0s",path_name);

However, if I made the path_name a reg and assigned it within an initial block, the display was correct:

reg [1023:0] path_name;
initial  path_name    = {chip_name,"module1.module2.signal"};

Can you use a reg instead of a wire?

Tim

Thanks Tim, but still with same issue: Non-string argument specified for $nc_mirror task...

You were right when you said that the path was empty, so I fixed it.

Now I mixed your solutions:

parameter [1023:0] chip_name="tb_top.I_0.";

reg [1023:0] path_name;

$nc_mirror("signal",path_name,"verbose");

With initial $display("signal %0s",path_name),  the path seems to be correct:

"tb_top.I_0.module1.module2.signal"

Any other idea?

How about using the string datatype as follows:

string chip_name = "tb_top.I_0.";
string path_name;
string full_path;

initial 
  begin
    path_name = "module1.module2.signal";
    full_path = {chip_name, path_name};
    $nc_mirror("signal", full_path, "verbose");  
  end

Hope that helps.

Mickey

Thanks Mickey.

string datatype is used in System Verilog right? How to enable it with ncsim 6.11? I tried with ncvlog -sv and it doesn't work.

Other options to solve my problem using normal Verilog? This is really important for me, since my database has plenty of those assignments...

.

No chance using string from System Verilog datatype.

ncvlog_cg: *W,NOSTRA: Non-string argument specified for $nc_mirror task at Line...

ncutils doesn't support the way to introduce signals as input parameters.

I was able to get it to work using the SV string datatype:

file test.sv

module test;

parameter /*[1023:0]*/ string chip_name="test.";

wire signal;
wire x,y;

/*reg [1023:0]*/ string path_name = {chip_name,"module2.a"};

module2 module2 (.a(x), .b(y));

initial begin
  $display("%0s",path_name);
  $nc_mirror("x",path_name,"verbose");
end

endmodule

file mod2.vhd

 library IEEE;                       -- IEEE library
use IEEE.std_logic_1164.all;        -- Reference the Std_logic_1164 system
use IEEE.numeric_std.all;           -- Reference numeric standard package

entity module2 is
  port(
    a   : in  std_logic;
    b   : out std_logic
  );
end module2;

architecture rtl of module2 is
  --signal data_bus_valid   : std_logic;

begin
  b <= a;
end rtl;

% irun -access rwc mod2.vhd test.sv

Although the string datatype is supported in IUS61, the above code did not work until IUS81.

Tim

So the problem is the current version of NC-Verilog, since the string problem appears when I have compiled/elaborated your code with irun.

Strange, since it seems to be last Cadence version.

irun: 06.11-s011: (c) Copyright 1995-2008 Cadence Design Systems:

ncvlog_cg: *W,NOSTRA: Non-string argument specified for $nc_mirror task at Line: 14 in File: ./test.sv.

Thanks Tpylant.