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System Verilog Assertions!!

Abraham Eapen

 Hi,

 I'm new to System Verilog & SVA. I've heard that its nearly like Verilog but with lots of enhancements and also that SVA's easy to learn.

Could anyone guide me how to write SVA coz I've got to write assertions for a variant of the SPI protocol for my project! How to start of writing assertions? SVA books are still not available here at my location. So any help from here would be very much appreciated.

Thx

  • Hi Abraham,

    SVA is not Verilog, it is an independent language added to the Verilog language and has the same learning effort as PSL. To learn writing assertions there are many places to start. It somewhat depends whether you want to simulate or formally verify the assertions. A few of them:

    • "Assertion Writing Guide" in the Incisive Release Documentation
    • "Assertion Quick-Start Guide" in the Incisive Release Documentation
    • IFV Basic Training (contains a SOP - EOP protocol example)
    • Examples from the IFV Methodology dosumentation
    • ...

    I recommend to contact your local Cadence AE in India, I am sure he is happy to assist you.

    Regards,
    Joerg.

  • As Joerg states, contacting your local AE would be a good next step. We already have an AEware set of assertions for SPI that they would be able to share with you. This would be an excellent way to get jump started.

     Chris

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