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digital simulation of design with FPGA

I need to run some simulations on a board design that includes and altera FPGA. I have the FPGA logic design done in quartus and have imported it into allegro in order to create a custom part. However I dont know how to set this up for simulation. The verilog file in the entity directory only includes the port declarations. What steps are needed to set this up for simulation including the internal FPGA logic. I am a student, can someone help me?

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