Connecting System Verilog to VHDL data type

Hello,

I am trying to instantiate a VHDL module inside a system verilog testbench.  The VHDL has a user defined type and system verilog not able to connect to it.  Any help is greatly appreciated.  Here is what the error and the code looks like.

Error "The type of VHDL port 'a' is invalid for Verilog connection"

Package ...

   TYPE real_vector_t           IS ARRAY (integer RANGE <>) OF real;

-------------------------------------------

ENTITY dut is
  PORT (
    -- input --
    A                 : in realr_vector(1 downto 0);
    B                   : out real
  );
END ENTITY dut;

ARCHITECTURE ams_real of dut is
BEGIN
END ARCHITECTURE ams_real;

Module dut_wrapper();

 real A[1:0];

real B;

 dut xdut(
   .A(A), 
   .B(B)
  );
endmodule: dut_wrapper

Thank you in advance.